Abstract—FinFET technology has been proposed as a promising alternative for deep sub-micron CMOS ... more Abstract—FinFET technology has been proposed as a promising alternative for deep sub-micron CMOS technology,because of its superior device performance, scalability, lower leakage power consumption and cost-effective fabricationprocess. Fin-type field-effect transistors (FinFETs) are capable substitutes for bulk CMOS at the nano-scale. Previous workshave studied the performance or power advantages of FinFET circuits over bulk CMOS circuits. This paper elucidates thedependability analysis of Average power, Leakage power, Leakage current and Delay of AND gate using double gateFinFET. Our experiments compare FinFET circuits at different voltages at 45 nm technology in virtuoso tool of cadence,showing that DG FinFET circuits have better dependability and scalability.
FinFET and its variants show great potential in scalability and manufacturability for nanoscale C... more FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS devices. In this paper we elucidate the design, fabrication, performance and integration issues of double-gate FinFET with the physical gate length and fin width being aggressively shrunk down to 10nm and 12nm respectively. This paper also deal with the various logic design styles to obtain the leakage power savings through the judicious use of FinFET logic styles using NAND based design. These MOSFETs are believed to be the smallest double-gate transistors ever fabricated and gives excellent short-channel performance in devices with a wide range of gate lengths.
International Conference on Control, Computing, Communication and Materials-2013
According to International Technology Roadmap for Semiconductors (ITRS) by the year 2014, 94% of ... more According to International Technology Roadmap for Semiconductors (ITRS) by the year 2014, 94% of chip area will be occupied by the memory. Aggressive scaling in memory can occur in two manners. One is the cell miniaturization, which can be achieved by device modeling. Other being the peripherals and interconnect scaling. Device scaling to nanoscale regime brings many problems which are sensitive to process variation. To enable the advancement of Silicon based technology, necessary to increase computing power and the manufacture of more compact circuits, significant changes to the current planar transistor are a necessity. Novel transistor architectures and materials are currently being researched vigorously. The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. In VLSI technology conventional CMOS transistors are continuously scaling down to obtain faster speed of devices and very large scale integrated circuits. However the main drawbacks of CMOS scaling are high leakage current and heavy channel doping. So that using CMOS beyond 45 nm cell stability and controlled leakage current are becoming difficult in today's fast low power applications. Double gate FinFET may be an alternative of conventional CMOS transistor. DG FinFET technology has been proposed as a promising alternative for deep sub-micron CMOS technology, because of its superior device performance, scalability, lower leakage power consumption and cost-effective fabrication process. Fin-type field-effect transistors (FinFETs) are capable substitutes for bulk CMOS at the nano-scale. Previous works have studied the performance or power advantages of FinFET circuits over bulk CMOS circuits. In principal, FinFETs with tall fins (large Hfin) can provide higher drive currents and smaller Vth variations than those with short fins (small Hfin) because of their increased channel width. This paper elucidates the dependability analysis of Average power, Leakage power, Leakage current and Delay of double gate FinFET. Our experiments compare FinFET circuits at different voltages at 45 nm technology in virtuoso tool of cadence, showing that DG FinFET circuits have better dependability and scalability.
International Conference on Emerging Research Areas and International Conference on Microelectronics, Communications and Renewable Energy (AICERA/ICMiCR), 2013 , Aug 2013
In this paper, we present analytical compact modelling approaches for the simulation of nanoscale... more In this paper, we present analytical compact modelling approaches for the simulation of nanoscale MOSFETs in which transport is dominated by ballistic high electron mobility transistors. A numerical method for the resolution of the two and three dimensional Poisson-Schrödinger equation is proposed and applied to the simulation of double gate n-MOSFET. We have also evaluated the mobility versus drain current relation for linear and saturated nanoscale MOSFET to the near-equilibrium mobility of carriers in long-channel MOSFET. Here transistor implementation of double gate n-MOSFET is done by using Virtuoso tool of cadence. Based on simulation results and analysis at 45 nm and 180 nm technology, some of the trade-offs are made in the design to improve the efficiency.
International Conference on Emerging Research Areas and International Conference on Microelectronics, Communications and Renewable Energy (AICERA/ICMiCR), 2013, Aug 2013
This Paper elucidate the development of SOI-MOSFET using different gates like single, double, tri... more This Paper elucidate the development of SOI-MOSFET using different gates like single, double, triple and gate all around structures. It is the Si MOSFET that is a fundamental device in the development of very high density Integrated Circuits. Thus SOI Technology is used for reducing the Parasitic Capacitances. Improvement in the electrostatic control by gate of the channel is done with the increase in effective number of gates. It minimizes short-channel effect which arises due to the lines of electric field from source and drain affecting control of the channel region. The technologies like Double-gate (top and bottom gate) SOI MOSFET and the Gate-all-Around (GAA) helps to suppress various short channel effects like Drain-Induced Barrier Lowering (DIBL) and degradation in Sub-threshold slope. Nano MOSFETs are now the requirements of nano electronics and it is the Gate- all-Around MOSFET which is employed in silicon Nano wires.
M. Ed - Thesis, Jiwaji University, Gwalior, M.P - June , 2018
The aim of this research is to investigate how a supportive relationship
between teachers and stu... more The aim of this research is to investigate how a supportive relationship between teachers and students in the classroom can improve the learning process. By having a good relationship with students, teachers can offer to student’s chances to be motivated and feel engaged in the learning process. Students will be engaged actively in the learning instead of being passive learners. I wish to investigate how using communicative approach and cooperative learning strategies while teaching do affect and improve students’ learning performance. To achieve these goals qualitative data collection was used as the primary method. The results show that teachers and students value a supportive and caring relationship between them and that interaction is essential to the teacher-student relationship. This sense of caring and supporting from teachers motivates students to become a more interested learner. Students benefit and are motivated when their teachers create a safe and trustful environment. And also the methods and strategies teachers uses, makes students feel engaged and stimulated to participate in the learning process. The students have in their mind that a positive relationship with their teachers positively impacts their interest and motivation in school which contributes to the enhancement of the learning process.
This project is a portable assembly of components and modules, which works on the same underlying... more This project is a portable assembly of components and modules, which works on the same underlying principles as its global counterpart “The Global Positioning System”. The G.P.S. consists of a constellation of satellites, which is used , in the navigation of an object (usually car or aircraft) anywhere in the world. Our L.P.S. works on the same lines and consists of a similar constellation of “Ultrasonic Transmitters And Receivers”. To exactly locate the position of an object with respect to a fixed reference within a restricted defined area. As the name of project suggest, it is basically about locating the position of a person room by room. As a model the project is handling two users simultaneously with three room locations to locate their positions. This tracking of users is done by means of two transmitter units that remain with users and three receiver units, one in each room. As the user moves in or out of a room, the information’s related to it like time in, time out, sending of buzzer calls etc can be monitored on a computer screen interfaced with three receivers through a connecting bus. The project can be extended to greater number of users as required by just duplicating the circuit. The circuitry involves simple components like Dip’s, resistors, transistors, FM transmitter & receivers etc. The software involves simple coding C++. Despite of all its simplicity the project finds wide range of applications in big institutes, universities, hospitals, offices & organisations.
According to International Technology Roadmap for Semiconductors (ITRS) by the year 2014, 94% of ... more According to International Technology Roadmap for Semiconductors (ITRS) by the year 2014, 94% of chip area will be occupied by the memory. Aggressive scaling in memory can occur in two manners. One is the cell miniaturization, which can be achieved by device modeling. Other being the peripherals and interconnect scaling. Device scaling to nanoscale regime brings many problems which are sensitive to process variation. To enable the advancement of Silicon based technology, necessary to increase computing power and the manufacture of more compact circuits, significant changes to the current planar transistor are a necessity. Novel transistor architectures and materials are currently being researched vigorously. The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. In VLSI technology conventional CMOS transistors are continuously scaling down to obtain faster speed of devices and very large scale integrated circuits. However the main drawbacks of CMOS scaling are high leakage current and heavy channel doping. So that using CMOS beyond 45 nm cell stability and controlled leakage current are becoming difficult in today's fast low power applications. Double gate FinFET may be an alternative of conventional CMOS transistor. DG FinFET technology has been proposed as a promising alternative for deep sub-micron CMOS technology, because of its superior device performance, scalability, lower leakage power consumption and cost-effective fabrication process. Fin-type field-effect transistors (FinFETs) are capable substitutes for bulk CMOS at the nano-scale. Previous works have studied the performance or power advantages of FinFET circuits over bulk CMOS circuits. In principal, FinFETs with tall fins (large Hfin) can provide higher drive currents and smaller Vth variations than those with short fins (small Hfin) because of their increased channel width. This paper elucidates the dependability analysis of Average power, Leakage power, Leakage current and Delay of double gate FinFET. Our experiments compare FinFET circuits at different voltages at 45 nm technology in virtuoso tool of cadence, showing that DG FinFET circuits have better dependability and scalability. Hence due to the above factors, FinFET technology has proposed as an alternative to deep submicron bulk CMOS. FinFET is likely to meet the performance requirements in the sub-45 nm gate length regime. FinFET will replace the traditional MOSFET due to its better performance in sub 45 nm regime and also it has excellent control over the problems faced by the Traditional CMOS. FinFET is also suitable for future nanoscale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current.
1. Educational Needs of Differently abled Children
2. Educational Administration
3. Women’s Educa... more 1. Educational Needs of Differently abled Children 2. Educational Administration 3. Women’s Education 4. Curriculum Development
PGDBA Thesis (HR) - Symbiosis Center For Distance Learning, Pune, 2015
Human resource management is concerned with people element in management. Since every
organizati... more Human resource management is concerned with people element in management. Since every organization is made up of people, acquiring their services, developing their skills/ motivating to high level of performances and ensuring that they continue to maintain their commitments to the organization which are essential to achieve organizational objectives. This project is meant to know the Recruitment and Selection Process by HR department. The HR Policies are a tool to achieve employee satisfaction and thus highly motivated employees. The main objective of various HR Policies is to increase efficiency by increasing motivation and thus fulfill organizational goals and objectives.
Abstract—FinFET technology has been proposed as a promising alternative for deep sub-micron CMOS ... more Abstract—FinFET technology has been proposed as a promising alternative for deep sub-micron CMOS technology,because of its superior device performance, scalability, lower leakage power consumption and cost-effective fabricationprocess. Fin-type field-effect transistors (FinFETs) are capable substitutes for bulk CMOS at the nano-scale. Previous workshave studied the performance or power advantages of FinFET circuits over bulk CMOS circuits. This paper elucidates thedependability analysis of Average power, Leakage power, Leakage current and Delay of AND gate using double gateFinFET. Our experiments compare FinFET circuits at different voltages at 45 nm technology in virtuoso tool of cadence,showing that DG FinFET circuits have better dependability and scalability.
FinFET and its variants show great potential in scalability and manufacturability for nanoscale C... more FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS devices. In this paper we elucidate the design, fabrication, performance and integration issues of double-gate FinFET with the physical gate length and fin width being aggressively shrunk down to 10nm and 12nm respectively. This paper also deal with the various logic design styles to obtain the leakage power savings through the judicious use of FinFET logic styles using NAND based design. These MOSFETs are believed to be the smallest double-gate transistors ever fabricated and gives excellent short-channel performance in devices with a wide range of gate lengths.
International Conference on Control, Computing, Communication and Materials-2013
According to International Technology Roadmap for Semiconductors (ITRS) by the year 2014, 94% of ... more According to International Technology Roadmap for Semiconductors (ITRS) by the year 2014, 94% of chip area will be occupied by the memory. Aggressive scaling in memory can occur in two manners. One is the cell miniaturization, which can be achieved by device modeling. Other being the peripherals and interconnect scaling. Device scaling to nanoscale regime brings many problems which are sensitive to process variation. To enable the advancement of Silicon based technology, necessary to increase computing power and the manufacture of more compact circuits, significant changes to the current planar transistor are a necessity. Novel transistor architectures and materials are currently being researched vigorously. The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. In VLSI technology conventional CMOS transistors are continuously scaling down to obtain faster speed of devices and very large scale integrated circuits. However the main drawbacks of CMOS scaling are high leakage current and heavy channel doping. So that using CMOS beyond 45 nm cell stability and controlled leakage current are becoming difficult in today's fast low power applications. Double gate FinFET may be an alternative of conventional CMOS transistor. DG FinFET technology has been proposed as a promising alternative for deep sub-micron CMOS technology, because of its superior device performance, scalability, lower leakage power consumption and cost-effective fabrication process. Fin-type field-effect transistors (FinFETs) are capable substitutes for bulk CMOS at the nano-scale. Previous works have studied the performance or power advantages of FinFET circuits over bulk CMOS circuits. In principal, FinFETs with tall fins (large Hfin) can provide higher drive currents and smaller Vth variations than those with short fins (small Hfin) because of their increased channel width. This paper elucidates the dependability analysis of Average power, Leakage power, Leakage current and Delay of double gate FinFET. Our experiments compare FinFET circuits at different voltages at 45 nm technology in virtuoso tool of cadence, showing that DG FinFET circuits have better dependability and scalability.
International Conference on Emerging Research Areas and International Conference on Microelectronics, Communications and Renewable Energy (AICERA/ICMiCR), 2013 , Aug 2013
In this paper, we present analytical compact modelling approaches for the simulation of nanoscale... more In this paper, we present analytical compact modelling approaches for the simulation of nanoscale MOSFETs in which transport is dominated by ballistic high electron mobility transistors. A numerical method for the resolution of the two and three dimensional Poisson-Schrödinger equation is proposed and applied to the simulation of double gate n-MOSFET. We have also evaluated the mobility versus drain current relation for linear and saturated nanoscale MOSFET to the near-equilibrium mobility of carriers in long-channel MOSFET. Here transistor implementation of double gate n-MOSFET is done by using Virtuoso tool of cadence. Based on simulation results and analysis at 45 nm and 180 nm technology, some of the trade-offs are made in the design to improve the efficiency.
International Conference on Emerging Research Areas and International Conference on Microelectronics, Communications and Renewable Energy (AICERA/ICMiCR), 2013, Aug 2013
This Paper elucidate the development of SOI-MOSFET using different gates like single, double, tri... more This Paper elucidate the development of SOI-MOSFET using different gates like single, double, triple and gate all around structures. It is the Si MOSFET that is a fundamental device in the development of very high density Integrated Circuits. Thus SOI Technology is used for reducing the Parasitic Capacitances. Improvement in the electrostatic control by gate of the channel is done with the increase in effective number of gates. It minimizes short-channel effect which arises due to the lines of electric field from source and drain affecting control of the channel region. The technologies like Double-gate (top and bottom gate) SOI MOSFET and the Gate-all-Around (GAA) helps to suppress various short channel effects like Drain-Induced Barrier Lowering (DIBL) and degradation in Sub-threshold slope. Nano MOSFETs are now the requirements of nano electronics and it is the Gate- all-Around MOSFET which is employed in silicon Nano wires.
M. Ed - Thesis, Jiwaji University, Gwalior, M.P - June , 2018
The aim of this research is to investigate how a supportive relationship
between teachers and stu... more The aim of this research is to investigate how a supportive relationship between teachers and students in the classroom can improve the learning process. By having a good relationship with students, teachers can offer to student’s chances to be motivated and feel engaged in the learning process. Students will be engaged actively in the learning instead of being passive learners. I wish to investigate how using communicative approach and cooperative learning strategies while teaching do affect and improve students’ learning performance. To achieve these goals qualitative data collection was used as the primary method. The results show that teachers and students value a supportive and caring relationship between them and that interaction is essential to the teacher-student relationship. This sense of caring and supporting from teachers motivates students to become a more interested learner. Students benefit and are motivated when their teachers create a safe and trustful environment. And also the methods and strategies teachers uses, makes students feel engaged and stimulated to participate in the learning process. The students have in their mind that a positive relationship with their teachers positively impacts their interest and motivation in school which contributes to the enhancement of the learning process.
This project is a portable assembly of components and modules, which works on the same underlying... more This project is a portable assembly of components and modules, which works on the same underlying principles as its global counterpart “The Global Positioning System”. The G.P.S. consists of a constellation of satellites, which is used , in the navigation of an object (usually car or aircraft) anywhere in the world. Our L.P.S. works on the same lines and consists of a similar constellation of “Ultrasonic Transmitters And Receivers”. To exactly locate the position of an object with respect to a fixed reference within a restricted defined area. As the name of project suggest, it is basically about locating the position of a person room by room. As a model the project is handling two users simultaneously with three room locations to locate their positions. This tracking of users is done by means of two transmitter units that remain with users and three receiver units, one in each room. As the user moves in or out of a room, the information’s related to it like time in, time out, sending of buzzer calls etc can be monitored on a computer screen interfaced with three receivers through a connecting bus. The project can be extended to greater number of users as required by just duplicating the circuit. The circuitry involves simple components like Dip’s, resistors, transistors, FM transmitter & receivers etc. The software involves simple coding C++. Despite of all its simplicity the project finds wide range of applications in big institutes, universities, hospitals, offices & organisations.
According to International Technology Roadmap for Semiconductors (ITRS) by the year 2014, 94% of ... more According to International Technology Roadmap for Semiconductors (ITRS) by the year 2014, 94% of chip area will be occupied by the memory. Aggressive scaling in memory can occur in two manners. One is the cell miniaturization, which can be achieved by device modeling. Other being the peripherals and interconnect scaling. Device scaling to nanoscale regime brings many problems which are sensitive to process variation. To enable the advancement of Silicon based technology, necessary to increase computing power and the manufacture of more compact circuits, significant changes to the current planar transistor are a necessity. Novel transistor architectures and materials are currently being researched vigorously. The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. In VLSI technology conventional CMOS transistors are continuously scaling down to obtain faster speed of devices and very large scale integrated circuits. However the main drawbacks of CMOS scaling are high leakage current and heavy channel doping. So that using CMOS beyond 45 nm cell stability and controlled leakage current are becoming difficult in today's fast low power applications. Double gate FinFET may be an alternative of conventional CMOS transistor. DG FinFET technology has been proposed as a promising alternative for deep sub-micron CMOS technology, because of its superior device performance, scalability, lower leakage power consumption and cost-effective fabrication process. Fin-type field-effect transistors (FinFETs) are capable substitutes for bulk CMOS at the nano-scale. Previous works have studied the performance or power advantages of FinFET circuits over bulk CMOS circuits. In principal, FinFETs with tall fins (large Hfin) can provide higher drive currents and smaller Vth variations than those with short fins (small Hfin) because of their increased channel width. This paper elucidates the dependability analysis of Average power, Leakage power, Leakage current and Delay of double gate FinFET. Our experiments compare FinFET circuits at different voltages at 45 nm technology in virtuoso tool of cadence, showing that DG FinFET circuits have better dependability and scalability. Hence due to the above factors, FinFET technology has proposed as an alternative to deep submicron bulk CMOS. FinFET is likely to meet the performance requirements in the sub-45 nm gate length regime. FinFET will replace the traditional MOSFET due to its better performance in sub 45 nm regime and also it has excellent control over the problems faced by the Traditional CMOS. FinFET is also suitable for future nanoscale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current.
1. Educational Needs of Differently abled Children
2. Educational Administration
3. Women’s Educa... more 1. Educational Needs of Differently abled Children 2. Educational Administration 3. Women’s Education 4. Curriculum Development
PGDBA Thesis (HR) - Symbiosis Center For Distance Learning, Pune, 2015
Human resource management is concerned with people element in management. Since every
organizati... more Human resource management is concerned with people element in management. Since every organization is made up of people, acquiring their services, developing their skills/ motivating to high level of performances and ensuring that they continue to maintain their commitments to the organization which are essential to achieve organizational objectives. This project is meant to know the Recruitment and Selection Process by HR department. The HR Policies are a tool to achieve employee satisfaction and thus highly motivated employees. The main objective of various HR Policies is to increase efficiency by increasing motivation and thus fulfill organizational goals and objectives.
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Papers by Aditya Dayal
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between teachers and students in the classroom can improve the learning process. By having a good relationship with students, teachers can offer to student’s chances to be motivated and feel engaged in the learning process. Students will be engaged actively in the learning instead of being passive learners. I wish to investigate how using communicative approach and cooperative learning strategies while teaching do affect and improve students’ learning performance. To achieve these goals qualitative data collection was used as the primary method. The results show that teachers and students value a supportive and caring relationship between them and that interaction is essential to the teacher-student relationship. This sense of caring and supporting from teachers motivates students to become a more interested learner. Students benefit and are motivated when their teachers create a safe and trustful environment. And also the methods and strategies teachers
uses, makes students feel engaged and stimulated to participate in the
learning process. The students have in their mind that a positive relationship with their teachers positively impacts their interest and motivation in school which contributes to the enhancement of the learning process.
As the name of project suggest, it is basically about locating the position of a person room by room. As a model the project is handling two users simultaneously with three room locations to locate their positions.
This tracking of users is done by means of two transmitter units that remain with users and three receiver units, one in each room. As the user moves in or out of a room, the information’s related to it like time in, time out, sending of buzzer calls etc can be monitored on a computer screen interfaced with three receivers through a connecting bus. The project can be extended to greater number of users as required by just duplicating the circuit.
The circuitry involves simple components like Dip’s, resistors, transistors, FM transmitter & receivers etc. The software involves simple coding C++.
Despite of all its simplicity the project finds wide range of applications in big institutes, universities, hospitals, offices & organisations.
Hence due to the above factors, FinFET technology has proposed as an alternative to deep submicron bulk CMOS. FinFET is likely to meet the performance requirements in the sub-45 nm gate length regime. FinFET will replace the traditional MOSFET due to its better performance in sub 45 nm regime and also it has excellent control over the problems faced by the Traditional CMOS. FinFET is also suitable for future nanoscale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current.
2. Educational Administration
3. Women’s Education
4. Curriculum Development
organization is made up of people, acquiring their services, developing their skills/ motivating
to high level of performances and ensuring that they continue to maintain their commitments to
the organization which are essential to achieve organizational objectives.
This project is meant to know the Recruitment and Selection Process by HR department. The
HR Policies are a tool to achieve employee satisfaction and thus highly motivated employees.
The main objective of various HR Policies is to increase efficiency by increasing motivation and
thus fulfill organizational goals and objectives.
between teachers and students in the classroom can improve the learning process. By having a good relationship with students, teachers can offer to student’s chances to be motivated and feel engaged in the learning process. Students will be engaged actively in the learning instead of being passive learners. I wish to investigate how using communicative approach and cooperative learning strategies while teaching do affect and improve students’ learning performance. To achieve these goals qualitative data collection was used as the primary method. The results show that teachers and students value a supportive and caring relationship between them and that interaction is essential to the teacher-student relationship. This sense of caring and supporting from teachers motivates students to become a more interested learner. Students benefit and are motivated when their teachers create a safe and trustful environment. And also the methods and strategies teachers
uses, makes students feel engaged and stimulated to participate in the
learning process. The students have in their mind that a positive relationship with their teachers positively impacts their interest and motivation in school which contributes to the enhancement of the learning process.
As the name of project suggest, it is basically about locating the position of a person room by room. As a model the project is handling two users simultaneously with three room locations to locate their positions.
This tracking of users is done by means of two transmitter units that remain with users and three receiver units, one in each room. As the user moves in or out of a room, the information’s related to it like time in, time out, sending of buzzer calls etc can be monitored on a computer screen interfaced with three receivers through a connecting bus. The project can be extended to greater number of users as required by just duplicating the circuit.
The circuitry involves simple components like Dip’s, resistors, transistors, FM transmitter & receivers etc. The software involves simple coding C++.
Despite of all its simplicity the project finds wide range of applications in big institutes, universities, hospitals, offices & organisations.
Hence due to the above factors, FinFET technology has proposed as an alternative to deep submicron bulk CMOS. FinFET is likely to meet the performance requirements in the sub-45 nm gate length regime. FinFET will replace the traditional MOSFET due to its better performance in sub 45 nm regime and also it has excellent control over the problems faced by the Traditional CMOS. FinFET is also suitable for future nanoscale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current.
2. Educational Administration
3. Women’s Education
4. Curriculum Development
organization is made up of people, acquiring their services, developing their skills/ motivating
to high level of performances and ensuring that they continue to maintain their commitments to
the organization which are essential to achieve organizational objectives.
This project is meant to know the Recruitment and Selection Process by HR department. The
HR Policies are a tool to achieve employee satisfaction and thus highly motivated employees.
The main objective of various HR Policies is to increase efficiency by increasing motivation and
thus fulfill organizational goals and objectives.