Journal of Inorganic and Organometallic Polymers and Materials, 2009
Magnetic SiC nanowires were obtained by the pyrolysis of iron containing polycarbosilane (PCS) wh... more Magnetic SiC nanowires were obtained by the pyrolysis of iron containing polycarbosilane (PCS) which in turn was synthesized by the reaction of polycarbosilane and iron (III) acetylacetonate [Fe(acac)3] in solvent. Characterization of synthesized polycarbosilane and Fe–SiC were performed with Fourier transformation infrared spectroscopy, energy dispersive X-ray spectrometry, powder X-ray diffraction, thermogravimetric analysis, scanning electron microscopy, electron spin resonance and vibrating sample magnetometer.
IEEE Transactions on Device and Materials Reliability, 2011
Abstract The degradation of nMOSFETs induced by nondestructive electrostatic discharge-like (ESD-... more Abstract The degradation of nMOSFETs induced by nondestructive electrostatic discharge-like (ESD-like) stress in a 32 nm bulk CMOS technology was studied using IV characteristics and charge pumping measurements. The impact of stress on drain saturation current ( ...
Catastrophic gate oxide breakdown of MOSFETs with high-k gate was characterized under ESD-like pu... more Catastrophic gate oxide breakdown of MOSFETs with high-k gate was characterized under ESD-like pulsed stress. It was found that the excessive gate current after gate oxide failure may result in a loss of gate contact and form a resistive path between the drain and source. Using constant voltage stress (CVS) method, the gate oxide breakdown voltages (VBD) of NMSOFETs and PMOSFETs were extracted. NMOSFETs under positive stress were found to have the smallest VBD, while the VBD of the PMOSFETs under positive stress were significantly increased due to the well resistance. Compared to that measured using the CVS method, the VBD from the transmission line pulse method (TLP) was smaller by only less than 10%. Despite the cumulative damages caused by the TLP method, the result is a conservative estimation of the breakdown voltage. The VBD corresponding to the failure time of 1-ns measured using TLP method agrees well with the extrapolation result from the CVS measurements on the time scale ranging from ~100 ns to ~20 μs, suggesting that the failure mechanism remains the same as in the longer time scale.
An ESD TCAD Workbench with a library of ESD and Latchup devices and circuits has been developed i... more An ESD TCAD Workbench with a library of ESD and Latchup devices and circuits has been developed in a 32nm bulk CMOS technology. The devices which were developed from process and layout information were calibrated to experimental results in the low current DC and high-current/high-temperature ESD regime. The failure currents of ESD devices correlated to the experimental data to within
We report pulsed high-k gate dielectric breakdown in various configurations emulating ESD stress ... more We report pulsed high-k gate dielectric breakdown in various configurations emulating ESD stress in real input/output circuits. The stress on the receiver is of greater concern than is stress on the driver due to different gate oxide areas under stress. Methods to improve pad voltage tolerance for gate oxide breakdown are proposed.
Abstract Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulato... more Abstract Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both ...
A comprehensive study on the interaction between ESD, NBTI and HCI on silicide blocked (SBLK) PFE... more A comprehensive study on the interaction between ESD, NBTI and HCI on silicide blocked (SBLK) PFET devices is presented for a state-of-the-art 65nm bulk technology. ESD behavior of thin and thick oxide devices are shown to have opposite channel length dependence. The study of NBTI-ESD interaction on thin oxides devices shows that non-destructive ESD pre-stressing worsens the NBTI degradation. On the other hand NBTI pre-stressed thick oxide devices show high on-resistance during ESD characterization. It is shown that in thin oxide long channel length devices at high temperature pure NBTI is the worst case degradation mode whereas in short channel length devices combined "HC-NBTI" degradation dominates. Furthermore, we observed that while a SBLK PFET is HC stressed at high temperature then NBTI also takes place simultaneously, resulting in "HC-NBTI" co-activation, which is found to be channel length dependent. Finally, we have shown that HC degradation is worse at high temperature than at room temperatures due to this NBTI co-activation.
Abstract We present technology scaling effects on the ESD performance of silicide-blocked PMOSFET... more Abstract We present technology scaling effects on the ESD performance of silicide-blocked PMOSFET devices. Stress elements and their effects are characterized using TLP and analyzed with the help of TCAD. Stress liners show no significant effect on ESD ...
Page 1. Technology Scaling of Advanced Bulk CMOS On-Chip ESD Protection down to the 32nm Node Jun... more Page 1. Technology Scaling of Advanced Bulk CMOS On-Chip ESD Protection down to the 32nm Node Junjun Li, Kiran Chatty, Robert Gauthier, Rahul Mishra, Christian Russ* IBM Semiconductor Research and Development Center, Essex Junction, VT 05452 USA ...
Journal of Inorganic and Organometallic Polymers and Materials, 2009
Magnetic SiC nanowires were obtained by the pyrolysis of iron containing polycarbosilane (PCS) wh... more Magnetic SiC nanowires were obtained by the pyrolysis of iron containing polycarbosilane (PCS) which in turn was synthesized by the reaction of polycarbosilane and iron (III) acetylacetonate [Fe(acac)3] in solvent. Characterization of synthesized polycarbosilane and Fe–SiC were performed with Fourier transformation infrared spectroscopy, energy dispersive X-ray spectrometry, powder X-ray diffraction, thermogravimetric analysis, scanning electron microscopy, electron spin resonance and vibrating sample magnetometer.
IEEE Transactions on Device and Materials Reliability, 2011
Abstract The degradation of nMOSFETs induced by nondestructive electrostatic discharge-like (ESD-... more Abstract The degradation of nMOSFETs induced by nondestructive electrostatic discharge-like (ESD-like) stress in a 32 nm bulk CMOS technology was studied using IV characteristics and charge pumping measurements. The impact of stress on drain saturation current ( ...
Catastrophic gate oxide breakdown of MOSFETs with high-k gate was characterized under ESD-like pu... more Catastrophic gate oxide breakdown of MOSFETs with high-k gate was characterized under ESD-like pulsed stress. It was found that the excessive gate current after gate oxide failure may result in a loss of gate contact and form a resistive path between the drain and source. Using constant voltage stress (CVS) method, the gate oxide breakdown voltages (VBD) of NMSOFETs and PMOSFETs were extracted. NMOSFETs under positive stress were found to have the smallest VBD, while the VBD of the PMOSFETs under positive stress were significantly increased due to the well resistance. Compared to that measured using the CVS method, the VBD from the transmission line pulse method (TLP) was smaller by only less than 10%. Despite the cumulative damages caused by the TLP method, the result is a conservative estimation of the breakdown voltage. The VBD corresponding to the failure time of 1-ns measured using TLP method agrees well with the extrapolation result from the CVS measurements on the time scale ranging from ~100 ns to ~20 μs, suggesting that the failure mechanism remains the same as in the longer time scale.
An ESD TCAD Workbench with a library of ESD and Latchup devices and circuits has been developed i... more An ESD TCAD Workbench with a library of ESD and Latchup devices and circuits has been developed in a 32nm bulk CMOS technology. The devices which were developed from process and layout information were calibrated to experimental results in the low current DC and high-current/high-temperature ESD regime. The failure currents of ESD devices correlated to the experimental data to within
We report pulsed high-k gate dielectric breakdown in various configurations emulating ESD stress ... more We report pulsed high-k gate dielectric breakdown in various configurations emulating ESD stress in real input/output circuits. The stress on the receiver is of greater concern than is stress on the driver due to different gate oxide areas under stress. Methods to improve pad voltage tolerance for gate oxide breakdown are proposed.
Abstract Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulato... more Abstract Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both ...
A comprehensive study on the interaction between ESD, NBTI and HCI on silicide blocked (SBLK) PFE... more A comprehensive study on the interaction between ESD, NBTI and HCI on silicide blocked (SBLK) PFET devices is presented for a state-of-the-art 65nm bulk technology. ESD behavior of thin and thick oxide devices are shown to have opposite channel length dependence. The study of NBTI-ESD interaction on thin oxides devices shows that non-destructive ESD pre-stressing worsens the NBTI degradation. On the other hand NBTI pre-stressed thick oxide devices show high on-resistance during ESD characterization. It is shown that in thin oxide long channel length devices at high temperature pure NBTI is the worst case degradation mode whereas in short channel length devices combined "HC-NBTI" degradation dominates. Furthermore, we observed that while a SBLK PFET is HC stressed at high temperature then NBTI also takes place simultaneously, resulting in "HC-NBTI" co-activation, which is found to be channel length dependent. Finally, we have shown that HC degradation is worse at high temperature than at room temperatures due to this NBTI co-activation.
Abstract We present technology scaling effects on the ESD performance of silicide-blocked PMOSFET... more Abstract We present technology scaling effects on the ESD performance of silicide-blocked PMOSFET devices. Stress elements and their effects are characterized using TLP and analyzed with the help of TCAD. Stress liners show no significant effect on ESD ...
Page 1. Technology Scaling of Advanced Bulk CMOS On-Chip ESD Protection down to the 32nm Node Jun... more Page 1. Technology Scaling of Advanced Bulk CMOS On-Chip ESD Protection down to the 32nm Node Junjun Li, Kiran Chatty, Robert Gauthier, Rahul Mishra, Christian Russ* IBM Semiconductor Research and Development Center, Essex Junction, VT 05452 USA ...
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