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BCH 2-Bit and 3-Bit Error Correction with Fast Multi-Bit Error Detection

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Architecture of Computing Systems (ARCS 2021)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 12800))

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Abstract

In this paper an new approach combining 2-bit and 3-bit BCH error correction with fast and simple error detection for errors of higher order is presented. Under the assumption that a 2-bit error or 3-bit error occurred, the corresponding correction bits are determined using the syndrome components \(s_1, s_3\) for 2-bit errors and \(s_1, s_3, s_5\) for 3-bit errors. These correction bits are used to calculate higher syndrome components up to \(s_{2T-1}\), which are compared to the actual corresponding syndrome components. If the syndrome components match, a 2-bit error or 3-bit error was detected. In the case of a syndrome mismatch, an error other than a 2-bit error or 3-bit error occurred and was detected. The proposed method provides a simple way to differentiate between 2-bit errors (3-bit errors) and errors of higher order.

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References

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Acknowledgment

I would like to thank Prof. Michael Gössel from the University of Potsdam for his stimulating discussions and remarks.

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Correspondence to Christian Schulz-Hanke .

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Schulz-Hanke, C. (2021). BCH 2-Bit and 3-Bit Error Correction with Fast Multi-Bit Error Detection. In: Hochberger, C., Bauer, L., Pionteck, T. (eds) Architecture of Computing Systems. ARCS 2021. Lecture Notes in Computer Science(), vol 12800. Springer, Cham. https://doi.org/10.1007/978-3-030-81682-7_13

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  • DOI: https://doi.org/10.1007/978-3-030-81682-7_13

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-81681-0

  • Online ISBN: 978-3-030-81682-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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