Abstract
For a typical digital system, the design process consists of compilation, translation, synthesis, logic optimization, and technology mapping. Although the final result of that process is a structure built of standard cells, logic cells, macroblocks, and similar components; the characteristics of the system (the silicon area, speed, power, etc.) depend considerably on the logic model of the digital system. Therefore, the synthesis and logic optimization has a significant impact on the quality of the implementation. In this chapter, we describe methods of designing and synthesis for logic controllers in novel reprogrammable structures with embedded memory blocks. This chapter is generally based on the ideas published in [5], however, a number of issues were extended and provide detailed information about the methods and algorithms used in the problem, including [6, 13, 14, 38]. The method starts with the formal specification of a logic controller behavior. To specify the complex nature of a logic controller we have chosen statechart diagrams [21]. The main advantage of this specification is the possibility of detecting all reachable deadlocks [26]. It is particularly important in the case of safety-critical systems since any failure of such system may cause injury or death to human beings. Having graphically specified the behavior, it is subsequently converted into a mathematical model [30]. Next, the mathematical model of the statechart is transformed into an equivalent finite state machine (FSM) [29]. Thus, the logic controller in FSM form can be synthesized by applying ROM-based decomposition method [6] or architectural decomposition method [13], and finally implemented in embedded memory block equipped architectures [45, 48]. Such architectures offer ability to update the functionality, partial reconfiguration, and low non-recurring engineering costs relative to an FPGA design.
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References
Adamski, M., Barkalov, A.: Architectural and sequential synthesis of digital devices. University of Zielona Góra, Zielona Góra (2006)
Baranov, S.I.: Logic synthesis for control automat. Kluwer Academic Publishers, Boston (1994)
Barkalov, A., Titarenko, L.: Logic synthesis for FSM-based control units, Lecture Notes in Electrical Engineering, vol. LNEE, vol. 53. Springer, Heidelberg (2009)
Bazydło, G., Adamski, M.: Logic controllers design from UML state machine diagrams. Czasopismo Techniczne: Informatyka z. 24, 3–18 (2008) (in Polish)
Borowik, G., Rawski, M., Łabiak, G., Bukowiec, A., Selvaraj, H.: Efficient logic controller design. In: Fifth International Conference on Broadband and Biomedical Communications (IB2Com), pp. 1–6 (December 2010), doi:10.1109/IB2COM.2010.5723633
Borowik, G.: Improved state encoding for FSM implementation in FPGA structures with embedded memory blocks. Electronics and Telecommunications Quarterly 54(1), 9–28 (2008)
Borowik, G., Kraśniewski, A.: Trading-off error detection efficiency with implementation cost for sequential circuits implemented with FPGAs. In: Moreno-Díaz, R., Pichler, F., Quesada-Arencibia, A. (eds.) EUROCAST 2011, Part II. LNCS, vol. 6928, pp. 327–334. Springer, Heidelberg (2012)
Borowik, G., Łuba, T., Tomaszewicz, P.: On memory capacity to implement logic functions. In: Moreno-Díaz, R., Pichler, F., Quesada-Arencibia, A. (eds.) EUROCAST 2011, Part II. LNCS, vol. 6928, pp. 343–350. Springer, Heidelberg (2012)
Brzozowski, J.A., Łuba, T.: Decomposition of boolean functions specified by cubes. Journal of Multi-Valued Logic and Soft Computing 9, 377–417 (2003)
Buchenrieder, K., Pyttel, A., Veith, C.: Mapping statechart models onto an FPGA-based ASIP architecture. In: EURO-DAC 1996, pp. 184–189 (September 1996), doi:10.1109/EURDAC.1996.558203
Bukowiec, A.: Synthesis of FSMs based on architectural decomposition with joined multiple encoding. International Journal of Electronics and Telecommunications 58(1), 35–41 (2012), doi:10.2478/v10177-012-0005-7
Bukowiec, A., Barkalov, A., Titarenko, L.: Encoding of internal states in synthesis and implementation process of automata into FPGAs. In: Proceedings of the Xth International Conference on the Experience of Designing and Application of CAD Systems in Microelectronics, CADSM 2009, pp. 199–201. Ministry of Education and Science of Ukraine and Lviv Polytechnic National University, Lviv, Publishing House Vezha & Co., Polyana, Ukraine (2009) ISBN: 978-966-2191-05-9
Bukowiec, A.: Synthesis of finite state machines for FPGA devices based on architectural decomposition. Lecture Notes in Control and Computer Science, vol. 13 (2009)
Bukowiec, A., Barkalov, A.: Structural decomposition of Finite State Machines. Electronics and Telecommunications Quarterly 55(2), 243–267 (2009)
Czerwiński, R., Kania, D.: State assignment for PAL-based CPLDs. In: Wolinski, C. (ed.) Proc. of 8th Euromicro Conference on Digital Systems Design, Architectures, Methods and Tools, Porto, Portugal, August 30-September 3, pp. 127–134. IEEE Computer Society (2005), doi:10.1109/DSD.2005.71
Doligalski, M.: Behavioral specification diversification for logic controllers implemented in FPGA devices. In: Proceedings of the 9th Annual FPGA Conference - FPGAworld 2012, Stockholm, Sweden, pp. 6:1–6:5. ACM (2012), doi:10.1145/2451636.2451642
Drusinsky, D., Harel, D.: Using statecharts for hardware description and synthesis. IEEE Transaction on Coputer-Aided Design 8(7), 798–807 (1989), doi:10.1109/43.31537
Drusinsky-Yoresh, D.: A state assignment procedure for single-block implementation of state chart. IEEE Transaction on Coputer-Aided Design 10(12), 1569–1576 (1991), doi:10.1109/43.103506
Gajski, D.D., Vahid, F., Narayan, S., Gong, J.: Specification and design of embedded systems. Prentice-Hall, Inc., Upper Saddle River (1994)
Gomes, L., Costa, A.: From use cases to system implementation: statechart based co-design. In: Proceedings of 1st ACM & IEEE Conference on Formal Methods and Programming Models for Codesign, MEMOCODE 2003, Mont Saint-Michel, France, pp. 24–33. IEEE Computer Society Press (2003), doi:10.1109/MEMCOD.2003.1210083
Harel, D.: Statecharts: A visual formalism for complex systems. Science of Computer Programming 8(3), 231–274 (1987), doi:10.1016/0167-6423(87)90035-9
Hartmanis, J., Stearns, R.E.: Algebraic structure theory of sequential machines. Prentice-Hall, New York (1966)
Henson, M.A.: Biochemical reactor modeling and control. IEEE Control Systems Magazine 26(4), 54–62 (2006), doi:10.1109/MCS.2006.1657876
I-Logix Inc., 3 Riverside Drive, Andover, MA 01810 U.S.A.: STATEMATE Magnum Code Generation Guide (2001)
Jenkins, J.H.: Designing with FPGAs and CPLDs. Prentice Hall, Upper Saddle River (1994)
Karatkevich, A.: Deadlock analysis in statecharts. In: Forum on Specification on Design Languages (2003)
Łabiak, G.: From UML statecharts to FPGA - the HiCoS approach. In: Proceedings of Forum on Specification & Design Languages, FDL 2003, pp. 354–363. Frankfurt am Main (September 2003)
Łabiak, G.: The use of hierarchical model of concurrent automaton in digital controller design. University of Zielona Góra Press, Poland, Zielona Góra (April 2005) (in Polish)
Łabiak, G.: From statecharts to FSM-description – transformation by means of symbolic methods. In: 3rd IFAC Workshop Discrete-Event System Design, DESDes 2006, Poland, pp. 161–166 (2006), doi:10.3182/20060926-3-PL-4904.00027
Łabiak, G., Borowik, G.: Statechart-based controllers synthesis in FPGA structures with embedded array blocks. Intl Journal of Electronic and Telecommunications 56(1), 11–22 (2010), doi:10.2478/v10177-010-0002-7
Łuba, T., Borowik, G., Kraśniewski, A.: Synthesis of Finite State Machines for implementation with programmable structures. Electronics and Telecommunications Quarterly 55(2) (2009)
de Micheli, G.: Symbolic design of combinational and sequentional logic circuits implemented by low-level logic macros. IEEE Transactions on CAD CAD-5(4), 597–616 (1986), doi:10.1109/TCAD.1986.1270230
de Micheli, G.: Synthesis and optimization of digital circuits. McGraw-Hill Higher Education (1994)
de Micheli, G., Brayton, R.K., Sangiovanni-Vincentelli, A.: Optimal state assignment for finite state machines. IEEE Transactions on CAD CAD-4(3), 269–284 (1985), doi:10.1109/TCAD.1985.1270123
Minato, S.: Binary decision diagrams and applications for VLSI CAD. Kluwer Academic Publishers, Boston (1996)
Ramesh, S.: Efficient translation of statecharts to hardware circuits. In: Twelfth International Conference on VLSI Design, pp. 384–389 (January 1999), doi:10.1109/ICVD.1999.745186
Rawski, M., Selvaraj, H., Łuba, T.: An application of functional decomposition in ROM-based FSM implementation in FPGA devices. Journal of Systems Architecture 51, 424–434 (2005), doi:10.1016/j.sysarc.2004.07.004
Rawski, M., Tomaszewicz, P., Borowik, G., Łuba, T.: 5 Logic synthesis method of digital circuits designed for implementation with embedded memory blocks of FPGAs. In: Adamski, M., Barkalov, A., Węgrzyn, M. (eds.) Design of Digital Systems and Devices. LNEE, vol. 79, pp. 121–144. Springer, Heidelberg (2011)
Sasao, T.: On the number of LUTs to realize sparse logic functions. In: Proc. of the 18th International Workshop on Logic and Synthesis, Berkeley, CA, U.S.A., July 31-August 2, pp. 64–71 (2009)
Szecówka, P.M., Pedzińska-Rżany, J., Wolczowski, A.R.: Hardware approach to artificial hand control based on selected DFT points of myopotential signals. In: Moreno-Díaz, R., Pichler, F., Quesada-Arencibia, A. (eds.) EUROCAST 2009. LNCS, vol. 5717, pp. 571–578. Springer, Heidelberg (2009)
Villa, T., Sangiovanni-Vincentelli, A.: NOVA: state assignment of finite state machines for optimal two-level logic implementation. IEEE Transactions on CAD 9(9), 905–924 (1990), doi:10.1109/43.59068
Yang, S.: Logic synthesis and optimization benchmarks User Guide Version 3.0. Tech. rep., Microelectronics Center of North Carolina, P.O. Box 12889, Research Triangle Park, NC 27709 (1991)
Zwolinski, M.: Digital system design with VHDL. Prentice Hall (2004)
Zydek, D., Selvaraj, H., Borowik, G., Luba, T.: Energy characteristic of processor allocator and network-on-chip. Journal of Applied Mathematics and Computer Science 21(2), 385–399 (2011), doi:10.2478/v10006-011-0029-7
Altera: Embedded Memory in Altera FPGAs (2010), http://www.altera.com/technology/memory/embedded/mem-embedded.html
FSMdec: FSMdec Homepage (2012), http://gborowik.zpt.tele.pw.edu.pl/node/58
HiCoS: HiCoS Homepage (2012), http://www.uz.zgora.pl/%7eglabiak
Xilinx: Block RAM (BRAM) Block (v1.00a), San Jose (August 2004), http://www.xilinx.com/support/documentation/ip_documentation/bram_block.pdf
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Borowik, G., Łabiak, G., Bukowiec, A. (2015). FSM-Based Logic Controller Synthesis in Programmable Devices with Embedded Memory Blocks. In: Klempous, R., Nikodem, J. (eds) Innovative Technologies in Management and Science. Topics in Intelligent Engineering and Informatics, vol 10. Springer, Cham. https://doi.org/10.1007/978-3-319-12652-4_8
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