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An Inter-Test Cube Bit Stream Connectivity-Optimized X-Filling Approach Aiming Shift Power Reduction

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International Conference on Intelligent Computing and Applications

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 632))

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Abstract

Transitions in scan cells bear much impact on the power consumption in scan-based VLSI test systems. X-filling approaches aim to fill don’t care bits of test cube by typically assigning binary values (i.e. either 1s or 0s) in such a way that the mean switching activity gets lessened. We propose here a new X-filling approach named as bit stream connectivity optimization-based X-filling technique, called BSCO—a technique to decrease average shift-in transitions crop up during scan-based testing. In our approach, we have not only considered the shift-in switching activity specific to test vectors but also minimized inter-test cube switching activity by applying BSCO approach. The experimental outcomes attained from the benchmark ISCAS’89 clearly shows that the method is effective for reducing average transitions during scan shift operation.

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References

  1. Girard P (2002) Survey of low-power testing of VLSI circuits. In IEEE Des. Test Computing, vol. 19, no. 3, pp. 82–92, doi:10.1109/MDT.2002.1003802

  2. Girard Patrick, Wen Xiaoqing, Touba Nur(2007). Low Power Testing. Morgan Kaufmann. System on-Chip Test Architectures: Nanometer Design for Testability, pp. 207–350, 978-0-12-373973-5

    Google Scholar 

  3. Wang Jing., Walker Duncan. M. H, Majhi A., Kruseman B., Gronthoud G., Villagra L. E., Wiel P. V. D. and Eichenberger S (2006) Power supply noise in delay testing. IEEE Design & Test of Computers. Volume: 24, No. 3, pp 226–234 doi:10.1109/MDT.2007.76

  4. Saxena Jaayasree, Butler Keneth. M., Jayaram Vinay. B. and Kundu S. (2003). A case study of IR-drop in structured at-speed testing, In Proceedings of IEEE International Test Conference (ITC), pp. 1098–1104 doi:10.1109/TEST.2003.1271098

  5. Wu F., Dilillo L., A. Bosio, Girard P., Pravossoudovitch S., Virazel A., J. Ma, W. Zhao, Tehranipoor M. and Wen X (2010) Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Fault Testing Schemes In Proc. of 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 376–381 doi:10.1109/DDECS.2010.5491748

  6. Butler Keneth M., Saxena Jaayasree., Jain A., Fryars T., Lewis J. and Hetherington G. (2004) Minimizing power consumption in scan testing: Pattern generation and DFT techniques, In proc. IEEE International Test Conference (ITC), pp. 355–364 doi:10.1109/TEST.2004.1386971

  7. Sankaralingam R., Pouya B. and Touba N. A. (2001) Reducing power dissipation during test using scan chain disable, in Proc. IEEE VLSI Test Symposium (VTS), 2001, pp. 319–324 doi:10.1109/VTS.2001.923456

  8. Xu Q., Hu D., and Xiang D (2007) Pattern-directed circuit virtual partitioning for test power reduction, in Proc. IEEE International Test Conference (ITC), pp 1–10 doi:10.1109/TEST.2007.4437633

  9. Lee K. J., Huang T. C. and Chen J. J (2000) Peak-power reduction for multiple-scan circuits during test application, in Proc. IEEE Asian Test Symposium (ATS), pp. 453–458 doi:10.1109/ATS.2000.893666

  10. Rosinger P. M., Al-Hashimi B.M. and Nicolici N (2004) “Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction,” IEEE Trans. Computer.-Aided Design Integration, Circuits Systems, vol. 23, no. 7, pp. 1142–1153 doi:10.1109/TCAD.2004.829797

  11. Lee K. J., Hsu S. J., and Ho C. M (2004) Test power reduction with multiple capture orders. In Proceedings of IEEE Asian Test Symposium (ATS), 2004, pp. 26–31 doi:10.1109/ATS.2004.82

  12. Bonhomme Y., Girard P., Landrault C., and Pravossoudovitch S. (2002) Power driven chaining of flip-flops in scan architectures, in Proc. IEEE International Test Conference (ITC), pp. 796–803 doi:10.1109/TEST.2002.1041833

  13. Bonhomme Y., Girard P, Guiller L., Landrault C. and Pravossoudovitch S (2003) “Efficient scan chain design for power minimization during scan testing under routing constraint,” in Proc. IEEE Int. Test Conf. (ITC), Vol 1, pp. 488–493 doi:10.1109/TEST.2003.1270874

  14. Li J., Hu Y. and Li X (2006) A scan chain adjustment technology for test power reduction. In Proc. 15th IEEE Asian Test Symposium (ATS) pp. 11–16 doi:10.1109/ATS.2006.260986

  15. Naeini M. M. and Ooi C. Y. (2015) A Novel Scan Architecture for Low Power Scan-Based Testing, VLSI Design, Vol. 2015, Article ID 264071, doi:10.1155/2015/264071

  16. Sankaralingam R. and Touba N. A. (2002) Inserting test points to control peak power during scan testing. In Proceedings of 17th IEEE International Symposium Defect Fault Tolerance VLSI Systems (DFT), pp. 138–146 doi:10.1109/DFTVS.2002.1173510

  17. Sharifi S., Jaffari J., Hosseinababy M., Afzali-Kusha A. and Navabi Z (2005) Simultaneous reduction of dynamic and static power in scan structures. In Proc. of Design Automation Test Eur. (DATE), pp. 846–851 doi:10.1109/DATE.2005.270

  18. Gerstendorfer S. and Wunderlich H. J. (1999) Minimized power consumption for scan-based BIST. In Proceedings of IEEE International Test Conf. (ITC), pp. 77–84 doi 10.1109/TEST.1999.805616

  19. Girard P., Guiller L., Landrault C. and Pravossoudovitch S (1999) Circuit partitioning for low power BIST design with minimized peak power consumption. In Proc. of IEEE Asian Test Symposium (ATS), pp. 89–94 doi:10.1109/ATS.1999.810734

  20. Basturkmen N. Z., Reddy S. M., and Pomeranz I (2002) A low power pseudo-random BIST technique, in Proc. Int. Conf. Comput. Des. (ICCD), pp. 468–473 doi:10.1109/ICCD.2002.1106815

  21. Bhunia S., Mahmoodi H., Ghosh D., Mukhopadhyay S. and Roy K. (2005) Low-power scan design using first-level supply gating. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 3, pp. 384–395 doi:10.1109/TVLSI.2004.842885

  22. Whetsel L.: Adapting scan architectures for low power operation, in Proc. IEEE International Test Conference (ITC), pp. 863–872 doi:10.1109/TEST.2000.894297

  23. Butler K. M., Saxena J., Fryars T., Hetherington G., Jain A., and Lewis J (2004) Minimizing power consumption in scan testing: Pattern generation and DFT techniques. In Proceedings International Test Conference, pp. 355–364 doi:10.1109/TEST.2004.1386971

  24. Song D., Ahn J., Kim T., and Kang S (2008) MTR-fill: A simulated annealing-based X- filling technique to reduce test power dissipation for scan-based designs, IEICE Transactions on Information and Systems, vol. E91-D, no. 4, pp. 1197–1200 doi:10.1093/ietisy/e91-d.4.1197

  25. Ghosh S., Basu S. and Touba N.A. (2003) Joint minimization of power and area in scan testing by scan cell reordering, In Proceedings. IEEE Computer Society Annual Symposium on VLSI, pp 246–249 doi:10.1109/ISVLSI.2003.1183485

  26. Li J. Xu Q., Hu Y., and Li X (2008) On reducing both shift and capture power for scan-based testing, in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC pp. 653–658 doi:10.1109/ASPDAC.2008.4484032

  27. Wen X., Yamashita Y., Morishima S., Kajihara S., Wang L., Saluja K. K. and Kinoshita K. (2005) Low-capture-power test generation for scan-based at-speed testing, in Proceedings International Test Conference, pp. 1019–1028. doi:10.1109/TEST.2005.1584068

  28. Sankaralingam R., Oruganti R. R. and Touba N.A (2000) Static compaction techniques to control scan vector power dissipation, in Proc. IEEE VLSI Test Symposium. (VTS), pp. 35–40 doi:10.1109/VTEST.2000.843824

  29. Synopsys Inc.: TetraMAX ATPG user Guide, 2006.

    Google Scholar 

  30. F. Brglez; D. Bryan and K. Kozminski (1989) Combinational profiles of sequential benchmark circuits, In IEEE International Symposium on Circuits and Systems, Vol 3, pp 1929–1934 doi:10.1109/ISCAS.1989.100747

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Authors and Affiliations

  1. Department of Computer Science and Engineering, Tripura Institute of Technology, Agartala, 799015, Tripura, India

    Sanjoy Mitra

  2. Department of Electronics and Communication Engineering, TSSOT, Assam University, Silchar, 788011, Assam, India

    Debaprasad Das

Authors
  1. Sanjoy Mitra
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  2. Debaprasad Das
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Correspondence to Sanjoy Mitra .

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Editors and Affiliations

  1. Department of Electrical and Electronics Engineering, SRM University, Chennai, Tamil Nadu, India

    Subhransu Sekhar Dash

  2. Electronics and Communication Sciences Unit, Indian Statistical Institute, Kolkata, West Bengal, India

    Swagatam Das

  3. Department of Electrical Engineering, Indian Institute of Technology Delhi, New Delhi, Delhi, India

    Bijaya Ketan Panigrahi

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Mitra, S., Das, D. (2018). An Inter-Test Cube Bit Stream Connectivity-Optimized X-Filling Approach Aiming Shift Power Reduction. In: Dash, S., Das, S., Panigrahi, B. (eds) International Conference on Intelligent Computing and Applications. Advances in Intelligent Systems and Computing, vol 632. Springer, Singapore. https://doi.org/10.1007/978-981-10-5520-1_44

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  • DOI: https://doi.org/10.1007/978-981-10-5520-1_44

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-5519-5

  • Online ISBN: 978-981-10-5520-1

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