Performance-Enhanced $d^2$-LBDR for 2D Mesh Network-on-Chip

Abstract

Growing demand for high-performance computing is necessitating faster on-chip communication. Network-on-Chip (NoC) with networking theory and methods for faster on-chip communication has emerged as a potential option. Due to transistor scaling down to sub-micron technologies, NoC also suffers from permanent or transient failures. Logic Based Distributed Routing (LBDR) has been proposed as a flexible fault tolerant routing implementation framework for Mesh-Based NoCs with link and router faults. The routing logic overhead remains invariant to the size of the topology making it scalable. LBDR is restricted to provide only minimal paths and can not support all failures. $d^2$-LBDR was developed to support non-minimal paths and thus would handle all single and double link permanent failures. Though, $d^2$-LBDR successfully covers all single and double link permanent failures but still restricts the available number of fault-free paths. In this paper, we present how this limitation on the available number of fault-free paths affects NoC performance. Based on our analysis, we present a new selection logic which enhances $d^2$-LBDR to explore all available fault-free paths. Our proposed solution having a marginal overhead in area and power provides higher performance ($7\%$ improvement in average flit latency and $4\%$ improvement in average network throughput when subject to two link faults in a 64-Node NoC).