Abstract
The Internet protocol version 6 which has an increase in address length with prefix length poses challenges in memory efficiency, incremental updates. So this work proposes adaptive optimal binary search tree (AOBT) based IPv6 lookup (AOBT-IL) architecture. An adaptive optimal binary search tree (AOBT) structure is introduced for the minimization of memory utilization. An Altera Quartus Stratix II device with Verilog HDL implements the IP lookup design. The proposed method performance is validated using different lookup table sizes with comparative analysis. The proposed method accomplished better outcomes in the case of maximum frequency, memory, SRAM, and logic elements results when compared to existing methods such as balanced parallelized frugal lookup (BPFL), linear pipelined IPv6 lookup architecture (IPILA) and parallel optimized linear pipeline (POLP) methods.
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Vijay, M.M., Shalini Punithavathani, D. (2022). A Memory-Efficient Adaptive Optimal Binary Search Tree Architecture for IPV6 Lookup Address. In: Shakya, S., Bestak, R., Palanisamy, R., Kamel, K.A. (eds) Mobile Computing and Sustainable Informatics. Lecture Notes on Data Engineering and Communications Technologies, vol 68. Springer, Singapore. https://doi.org/10.1007/978-981-16-1866-6_57
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