Abstract
Microprocessors without interlocked stages (MIPS) are based on the reduced instruction set computer architecture. These processors have been in use for years and remain in wide use today in applications such as automation, processing, and communication. Many of these applications must be run on smaller, low-cost target boards with limited resources. Field-programmable gate arrays (FPGAs) are also gaining importance in the very large scale integration design flows because their parallel architecture makes them very fast. Some low-cost FPGAs also offer limited on chip resources such as lookup tables and flip flops. Furthermore, high-level synthesis is gaining popularity among designers because it offers a higher level of design abstraction along with continued verification during the design flow. In this paper, we propose a low-area MIPS processor with high throughput. We use high-level synthesis to generate register transfer level code for the 32-bit MIPS core and target the same for Virtex 7 FPGA. We optimize the design for area and performance using selected high-level synthesis directives, which produces results superior to those reported in the literature.
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References
O. Indira, V.V. Dwivedi, M. Kamaraju, Verilog implementation of a MIPS RISC 32-bit pipelined processor architecture. IOSR J. Electron. Commun. Eng. 14, 31–40 (2019)
R.F. Olanrewaju, F.E. Fajingbesi, S.B. Junaid, R. Alahudin, F. Anwar, B.R. Pampori, Design and implementation of a 5-stage pipelining architecture simulator for RISC-16 instruction set. Indian J. Sci. Technol. 10, 1–9 (2017)
H.S. Bhimani, H.N. Patel, A.A. Davda, Design of 32-bit 3-stage pipelined processor based on MIPS in Verilog HDL and implementation on FPGA Virtex7. Int. J. Appl. Inf. Syst. 10 (2016)
S. Mangalwedhe, R. Kulkarni, S.Y. Kulkarni, Low power implementation of 32-bit RISC processor with pipelining, in Proceeding of the Second International Conference on Microelectronics. Lecture Notes in Electrical Engineering (2019), pp. 307–320. https://doi.org/10.1007/978-981-10-8234-4_27
M.R. Rakesh, B. Ajeya, A.R. Mohan, Novel architecture of 17 bit address RISC CPU with pipelining technique using Xilinx in VLSI technology. Int. J. Eng. Res. Appl. 4, 116–121 (2014)
F. Ghenassia, Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems (Springer, The Netherlands, 2005)
Xilinx, Vivado Design Suite: High-Level Synthesis (2018). Available from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug902-vivado-high-level-synthesis.pdf
Math Works, HDL Coder. Available from: https://www.mathworks.com/products/hdl-coder.html
K. Wakabayashi, C-based behavioral synthesis and verification analysis on industrial design examples, in Proceedings of the ASPDAC (2004), pp. 344–348
K. Kucukcakar, C.-T. Chen, J. Gong, W. Philipsen, T.E. Tkacik, Matisse: an architectural design tool for commodity ICs. IEEE Des. Test Comput. 15, 22–33 (1998). https://doi.org/10.1109/54.679205
R.A. Bergamaschi, R.A. O’Connor, L. Stok, M.Z. Moricz, S. Prakash, A. Kuehlmann, D.S. Rao, High-level synthesis in an industrial environment. IBM J. Res. Dev. 39, 131–148 (1995). https://doi.org/10.1147/rd.391.0131
P.E. Lippens, J.L. van Meerbergen, A. van der Werf, W.F. Verhaegh, B.T. McSweeney, J.O. Huisken, O.P. McArdle, PHIDEO: a silicon compiler for high speed algorithms, in Proceedings of the European Conference Design Auto (IEEE Computer Society Press, Amsterdam, 1991), pp. 436–441
J. Biesenack, M. Koster, A. Langmaier, S. Ledeux, S. Marz, M. Payer, M. Pilsl, S. Rumler, H. Soukup, N. Wehn, P. Duzy, The Siemens high-level synthesis system CALLAS. IEEE Trans. Very Large Scale Integr. 1, 244–253 (1993). https://doi.org/10.1109/92.238438
D.W. Knapp, Behavioral Synthesis: Digital System Design Using the Synopsys Behavioral Compiler (Prentice Hall, Englewood Cliffs, NJ, 1996)
Catapult, High-Level Synthesis (2020). Available from: https://www.mentor.com/hls-lp/catapult-high-level-synthesis/
Stratus High-Level Synthesis. Available from: https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html
J. Hennessy, N. Jouppi, F. Baskett, J. Gill, MIPS: A VLSI Processor Architecture (Springer, Berlin, Heidelberg; Stanford University, Departments of Electrical Engineering and Computer Science, 1981), pp. 337–346
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Sikka, P., Asati, A.R., Shekhar, C. (2022). Low-Area, High-Throughput Field-Programmable Gate Array Implementation of Microprocessor Without Interlocked Pipeline Stages. In: Dhawan, A., Tripathi, V.S., Arya, K.V., Naik, K. (eds) Recent Trends in Electronics and Communication. VCAS 2020. Lecture Notes in Electrical Engineering, vol 777. Springer, Singapore. https://doi.org/10.1007/978-981-16-2761-3_58
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DOI: https://doi.org/10.1007/978-981-16-2761-3_58
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