Abstract
In this paper, basic logic gates are designed at 10 nm technology node using Fin Field Effect Transistor (FinFET), and comparative analysis is performed with the proposed one based on input dependent (INDEP) technique. The total power dissipation in case of FinFET INDEP NAND gate and FinFET INDEP NOR gate is reduced by 63.28 and 66.08%, while power delay product is reduced by 63.26% and 50.06%, respectively, in comparison with the FinFET NAND and NOR gate without INDEP technique. Comparative analysis is also performed between INDEP FinFET inverters with the one without INDEP technique. The simulation results show that the design of logic gates using INDEP FinFET is more efficient in comparison with the one without technique. The reliability of the logic gates is also checked using Monte Carlo approach which clearly depicts the improved performance parameters of FinFET logic gates designed using INDEP technique.
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Mushtaq, U., Akram, M.W., Prasad, D. (2022). Design and Analysis of Energy-Efficient Logic Gates Using INDEP Short Gate FinFETs at 10 nm Technology Node. In: Chakravarthy, V.V.S.S.S., Flores-Fuentes, W., Bhateja, V., Biswal, B. (eds) Advances in Micro-Electronics, Embedded Systems and IoT. Lecture Notes in Electrical Engineering, vol 838. Springer, Singapore. https://doi.org/10.1007/978-981-16-8550-7_3
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DOI: https://doi.org/10.1007/978-981-16-8550-7_3
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