Abstract
Static random access memory (SRAM) is one of the key components in the growing embedded systems with a demand in its increased capacity. It is necessary to do power analysis at the early stages of the design process for such large sized SRAMs to avoid further complexities that degrade system performance to worst. SRAMs are greatly delved from 6T to 10T with its size against to the read and write stability issues. However, use of 10T alone in the large sized memories is not feasible for the low-power system architectures. In this paper, a unique style of dual-port hybrid SRAM memory architectures is proposed using different combinations of 6T and 7T. The hybrid model using 6T-7T SRAM cell is performing well over traditional 6T-6T and 7T-7T architectures with power reduction improvement of 27.2% and 30.5%, respectively, and with area reduction improvement of 26.1% and 8.15%, respectively.
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Parvathi, M., Chinnaaiah, M.C. (2023). Implementation and Performance Evaluation of Hybrid SRAM Architectures Using 6T and 7T for Low-Power Applications. In: Bhateja, V., Mohanty, J.R., Flores Fuentes, W., Maharatna, K. (eds) Communication, Software and Networks. Lecture Notes in Networks and Systems, vol 493. Springer, Singapore. https://doi.org/10.1007/978-981-19-4990-6_22
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DOI: https://doi.org/10.1007/978-981-19-4990-6_22
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