Abstract
The authors present an analysis of various clock gating techniques and its power requirements considering an application. Whenever the number of transistors to be mounted on single chip enhances, need for power optimization increases in the same pace. In the design of SoC, the reduction of power plays a vital role. When considered in sequential design source of power consumption is dynamic power. The clock gating technique reduces this dynamic clock to larger extent. In this paper, authors have implemented various clock gating techniques on test circuit. Power analysis is carried out using X-power analyzer to study the power optimization. From experimental results, it is observed that autogated clock gating technique consumes 68.63% power when compared with design under test without clock gating technique.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Yeap GK (2012) Practical low power digital VLSI design. Springer Science & Business Media
Sharma DK (2012) Effects of different clock gating techniques on design. Int J Sci Eng Res 3(5)
Schoenmakers PJ, Theeuwen JFM (1998) Clock gating on RT-level VHDL. In: Proceedings of the international workshop on logic synthesis, pp 7–10
Srinivasan N, Prakash NS, Shalakha D, Sivaranjani D, Sundari BBT (2015) Power reduction by clock gating technique. Procedia Technol 21:631–635
Dev MP, Baghel D, Pandey B, Pattanaik M, Shukla A (2013) Clock gated low power sequential circuit design. In: 2013 IEEE conference on information and communication technologies. IEEE, pp 440–444
Anand N, Joseph G, Oommen SS (2014) Performance analysis and implementation of clock gating techniques for low power applications. In: 2014 International conference on science engineering and management research (ICSEMR). IEEE, pp 1–4
Shinde J, Salankar SS (2011) Clock gating—a power optimizing technique for VLSI circuits. In: 2011 Annual IEEE India conference. IEEE, pp 1–4
Kaushik PG, Gulhane SM, Khan AR (2013) Dynamic power reduction of digital circuits by clock gating. Int J Adv Technol 4(1):79–88
Shanmugasundaram N (2018) Clock gating techniques: an overview. In: 2018 Conference on emerging devices and smart systems (ICEDSS). IEEE, pp 217–221
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2024 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Bhajantri, A., Budihal, S., Siddamal, S.V. (2024). Analysis of Clock Gating Techniques for Low Power. In: Chakravarthy, V.V.S.S.S., Bhateja, V., Anguera, J., Urooj, S., Ghosh, A. (eds) Advances in Microelectronics, Embedded Systems and IoT. ICMEET 2023. Lecture Notes in Electrical Engineering, vol 1156. Springer, Singapore. https://doi.org/10.1007/978-981-97-0767-6_5
Download citation
DOI: https://doi.org/10.1007/978-981-97-0767-6_5
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-97-0766-9
Online ISBN: 978-981-97-0767-6
eBook Packages: EngineeringEngineering (R0)