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Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications

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Abstract

This paper presents a multiplying delay-locked loop (MDLL) embedded with a frequency-only reference (FREF) based fully digital low-dropout regulator (DLDO) that outperforms conventional dynamic voltage and frequency scaling circuits when driving digital-load circuits that operate down to the near-threshold voltage level . We also propose a feed-forward acceleration (FFA) technique, which is dynamically activated only during the transient period to reduce the transient response time and voltage droop caused by the load current step. The proposed DLDO-embedded-MDLL was fabricated in a 40 nm CMOS process and occupies an active area of 0.02 mm2. At the typical VIN = 1.2 V and FREF = 37.4 MHz, the regulated range of voltage was measured to be 0.56–1.16 V while the frequency being scaled from 0.411 to 2.35 GHz. With the proposed FFA technique, the load transient response and voltage droop were reduced by 61.5 and 35%, respectively, compared to the values during normal loop operation. In addition, the measured phase noise at 0.411 and 2.35 GHz was less than −116 and −104 dBc/Hz, respectively, both at 1 MHz offset.

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Acknowledgements

This research was supported partly by the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2017R1A2B4012203).

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Authors and Affiliations

  1. Department of Electrical and Electronics Engineering, Kangwon National University, Room No. 201, Building No. 102, Hyoja-dong, Chunchoen, Korea

    Muhammad Abrar Akram & In-Chul Hwang

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  1. Muhammad Abrar Akram
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  2. In-Chul Hwang
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Correspondence to In-Chul Hwang.

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Akram, M.A., Hwang, IC. Fully digital fast transient phase-locked digital LDO-embedded-MDLL for DVFS applications. Analog Integr Circ Sig Process 93, 123–136 (2017). https://doi.org/10.1007/s10470-017-1028-x

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  • DOI: https://doi.org/10.1007/s10470-017-1028-x

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