Abstract
Analog-to-digital converters (ADCs) are an important component in electronics design. One of the difficulties being faced is to be able to accurately and cost-effectively test the continually higher performance of ADCs under budget constraints. Test time for static linearity is a major portion of the total test cost. Our group proposed an ultrafast segmented model identification of linearity error (uSMILE) algorithm for estimating linearity, which reduces test time dramatically compared to the conventional method. However, this algorithm produces large estimation errors in low resolution ADCs (10-12 bits) when the input is a ramp signal, for which the quantization noise of ADC becomes a dominant part in the total noise. In this study, we propose three types of distribution dithering methods added to the ramp input signal to reduce the estimation error when uSMILE was applied to low resolution ADCs. Fixed pattern was proved to be the most efficient and cost-effective method by comparing with the Gaussian, uniform, and fixed-pattern distributions. The simulation results indicate that the estimation error can be significantly reduced in a 12-bit SAR ADC with effective dithering. Furthermore, a hardware evaluation board with commercial ADC products was used to validate the effectiveness of the fixed-pattern dithering methods, and our measurement shows the INL estimation error can be reduced to less than 0.1 LSB. Such dithering method relaxes the input requirement of uSMILE algorithm which dramatically reduces the test setup cost.
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Appendix: Derivation of Eq. 4 in Section 2
Appendix: Derivation of Eq. 4 in Section 2
Let N M S B , N I S B and N L S B be the numbers of bits in MSB, ISB and LSB bits. Then, the numbers of segments are \(2^{N_{MSB}}\), \(2^{N_{ISB}}\) and \(2^{N_{LSB}}\) for MSB, ISB and LSB segments respectively. Define E M in Eq. 13 is a column matrix of all the error terms of MSB E M terms. E I and E L are defined similarly.
Define three matrices H M ,H I and H L . H M in Eq. 14 is a \(k*2^{M_{LSB}}\) matrix with each term being a boolean value either one or zero. k is the total sample number of input data. Each row represents each sample falling in MSB error term E M . If the MSB error term of the j t h sample data corresponds to E M (X), then the X t h column of the H M is one in j t h row. It is the only one in each row and all the others are zeros in corresponding row. H I and H L are defined in the same way for ISB and LSB bits.
Then, the estimated INL for the whole sample can be expressed as Eq. 15.
In the (i + 1) t h column in the matrix, we multiplied both sides by the transpose of this column matrix.
In this matrix \(\left [\begin {array}{ll} C_{MSB}(1) == i \ \ {\cdots } \ \ C_{MSB}(k) ==i \end {array}\right ] \), only the location where the corresponding MSB bit being i will be 1s and all the other all 0s. Therefore, 17 can be obtained.
If the total number of samples is k, within each MSB segment, the number of samples is approximately equal to \(k/2^{N_{MSB}}\) . Within each MSB segment, the number of samples for each ISB segment is approximately equal to \(k/2^{(N_{MSB}+N_{ISB})}\) . Within each MSB segment, the number of samples for each LSB segment is approximately equal to \(k/2^{(N_{MSB}+N_{ISB})}\) . Then, Eq. 17 can be approximated by Eq. 18.
In this equation, \({\sum }_{j = 0}^{N_{ISB}-1} (E_{I}(j))\) and \({\sum }_{j = 0}^{N_{LSB}-1} (E_{L}(j))\) are close to 0 and their coefficients are also much smaller compared with the number of C M S B equal to i so that the last two terms are almost 0 and can be discarded shown in Eq. 19.
Dividing both sides by the number of MSB bits being (# C M S B == i), we obtained the Eq. 20
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Duan, Y., Chen, T. & Chen, D. A Low-cost Dithering Method for Improving ADC Linearity Test Applied in uSMILE Algorithm. J Electron Test 33, 709–720 (2017). https://doi.org/10.1007/s10836-017-5696-3
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DOI: https://doi.org/10.1007/s10836-017-5696-3