Abstract
Analog/RF alternate test schemes have been extensively studied in the past decade with the goal of replacing time-consuming and expensive specification tests with low-cost alternate measurements. A common approach in analog/RF alternate test is to build non-linear regression models to map the specification tests to alternate measurements, or to learn a pass/fail separation boundary directly in the space of alternate measurements. Among various challenges that have been discussed in alternate test, the model stationarity is a major bottle-neck that prevents test engineers from deploying it in long-term applications. In this work, we show that alternate test strategies can be implemented on-chip using analog/RF Built-In Self-Test (BIST) circuitry. Moreover, model refinement and dynamic adaptation can be achieved based on an automatic on-chip learning structure. Effectiveness of the proposed approach is demonstrated using experimental results from an RF Low Noise Amplifier (LNA) and its BIST implementation.
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Kansara, P., Reddy, S.B., Abdallah, L. et al. Dynamic Analog/RF Alternate Test Strategies Based on On-chip Learning. J Electron Test 34, 337–349 (2018). https://doi.org/10.1007/s10836-018-5724-y
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DOI: https://doi.org/10.1007/s10836-018-5724-y