Abstract
Three-dimensional integrated circuit (3D-IC) has emerged as a savior of failing Moore’s law, where reduced length of interconnects is guaranteed with some added advantages like heterogeneous integration, higher computation per volume, etc. These benefits are also exhibited in 3D SoCs (3D System on Chips) to use the already built cores. However, testing these large complex SoCs in lesser time has become a challenge. In this work, we propose a simulated annealing-based wrapper chain design algorithm that will balance the length of the wrapper chain. The number of TSVs (Through Silicon Vias) is also kept as a constraint so that the number of TSVs could also be reduced. Rigorous experiments were conducted on several ITC’02 SoC benchmark and the results when compared with a recent work which showed that our proposed approach recorded better test lengths in more than 90% cases with an average reduction of 6.42% in test length. Our algorithms also used less number of TSVs in approximately 90% of the cases with an average reduction of 23.82% in the number of TSVs, in comparable CPU time.
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Banerjee, S., Ghorui, S. & Majumder, S. Designing balanced wrapper chains in 3D SoC under constrained TSVs. Innovations Syst Softw Eng 17, 219–230 (2021). https://doi.org/10.1007/s11334-021-00402-w
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DOI: https://doi.org/10.1007/s11334-021-00402-w