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Cryptographic Hardware and Embedded Systems - CHES 2005

7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings

  • Conference proceedings
  • © 2005

Overview

Editors:
  1. Josyula R. Rao

    1. IBM Watson Research Center, Yorktown Heights, USA

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    You can also search for this editor in PubMed   Google Scholar

  2. Berk Sunar

    1. Cryptography & Information Security Laboratory, WPI, Worcester, USA

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 3659)

Part of the book sub series: Security and Cryptology (LNSC)

Included in the following conference series:

Conference proceedings info: CHES 2005.

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Table of contents (32 papers)

  1. Front Matter

    Download chapter PDF

  2. Side Channels I

    1. Resistance of Randomized Projective Coordinates Against Power Analysis

      • William Dupuy, Sébastien Kunz-Jacques
      Pages 1-14

    2. Templates as Master Keys

      • Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi, Kai Schramm
      Pages 15-29

    3. A Stochastic Model for Differential Side Channel Cryptanalysis

      • Werner Schindler, Kerstin Lemke, Christof Paar
      Pages 30-46

  3. Arithmetic for Cryptanalysis

    1. A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis

      • Jean Sébastien Coron, David Lefranc, Guillaume Poupard
      Pages 47-60

    2. Further Hidden Markov Model Cryptanalysis

      • P. J. Green, R. Noad, N. P. Smart
      Pages 61-74

  4. Low Resources

    1. Energy-Efficient Software Implementation of Long Integer Modular Arithmetic

      • Johann Großschädl, Roberto M. Avanzi, Erkay SavaÅŸ, Stefan Tillich
      Pages 75-90

    2. Short Memory Scalar Multiplication on Koblitz Curves

      • Katsuyuki Okeya, Tsuyoshi Takagi, Camille Vuillaume
      Pages 91-105

    3. Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 μP

      • Lejla Batina, David Hwang, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede
      Pages 106-118

  5. Special Purpose Hardware

    1. SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers

      • Jens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl, Christine Priplata, Colin Stahlke
      Pages 119-130

    2. Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization

      • Willi Geiselmann, Adi Shamir, Rainer Steinwandt, Eran Tromer
      Pages 131-146

    3. Design of Testable Random Bit Generators

      • Marco Bucci, Raimondo Luzzi
      Pages 147-156

  6. Hardware Attacks and Countermeasures I

    1. Successfully Attacking Masked AES Hardware Implementations

      • Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald
      Pages 157-171

    2. Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints

      • Thomas Popp, Stefan Mangard
      Pages 172-186

    3. Masking at Gate Level in the Presence of Glitches

      • Wieland Fischer, Berndt M. Gammel
      Pages 187-200

  7. Arithmetic for Cryptography

    1. Bipartite Modular Multiplication

      • Marcelo E. Kaihara, Naofumi Takagi
      Pages 201-210

    2. Fast Truncated Multiplication for Cryptographic Applications

      • Laszlo Hars
      Pages 211-225

    3. Using an RSA Accelerator for Modular Inversion

      • Martin Seysen
      Pages 226-236

    4. Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings

      • B. Sunar, D. Cyganski
      Pages 237-249

  8. Side Channel II (EM)

    1. EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA

      • Catherine H. Gebotys, Simon Ho, C. C. Tiu
      Pages 250-264
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  1. Cryptographic Hardware and Embedded Systems – CHES 2005

Editors and Affiliations

  • IBM Watson Research Center, Yorktown Heights, USA

    Josyula R. Rao

  • Cryptography & Information Security Laboratory, WPI, Worcester, USA

    Berk Sunar

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