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Formal Methods in Computer-Aided Design

4th International Conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings

  • Conference proceedings
  • © 2002

Overview

Editors:
  1. Mark D. Aagaard

    1. Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Canada

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    You can also search for this editor in PubMed   Google Scholar

  2. John W. O’Leary

    1. Strategic CAD Labs, Intel Corporation, Hillsboro, USA

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 2517)

Included in the following conference series:

Conference proceedings info: FMCAD 2002.

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About this book

This volume contains the proceedings of the Fourth Biennial Conference on F- mal Methods in Computer-Aided Design (FMCAD). The conference is devoted to the use of mathematical methods for the analysis of digital hardware c- cuits and systems. The workreported in this bookdescribes the use of formal mathematics and associated tools to design and verify digital hardware systems. Functional veri?cation has become one of the principal costs in a modern computer design e?ort. FMCAD provides a venue for academic and industrial researchers and practitioners to share their ideas and experiences of using - screte mathematical modeling and veri?cation. Over the past 20 years, this area has grown from just a few academic researchers to a vibrant worldwide com- nity of people from both academia and industry. This volume includes 23 papers selected from the 47 submitted papers, each of which was reviewed by at least three program committee members. The history of FMCAD dates backto 1984, when the earliest meetings on this topic occurred as part of IFIP WG10.2.

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Table of contents (23 papers)

  1. Front Matter

    Pages I-XI
    Download chapter PDF

  2. Abstraction

    1. Abstraction by Symbolic Indexing Transformations

      • Thomas F. Melham, Robert B. Jones
      Pages 1-18

    2. Counter-Example Based Predicate Discovery in Predicate Abstraction

      • Satyaki Das, David L. Dill
      Pages 19-32

    3. Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis

      • Pankaj Chauhan, Edmund Clarke, James Kukula, Samir Sapra, Helmut Veith, Dong Wang
      Pages 33-51

  3. Symbolic Simulation

    1. Simplifying Circuits for Formal Verification Using Parametric Representation

      • In-Ho Moon, Hee Hwan Kwak, James Kukula, Thomas Shiple, Carl Pixley
      Pages 52-69

    2. Generalized Symbolic Trajectory Evaluation — Abstraction in Action

      • Jin Yang, Carl-Johan H. Seger
      Pages 70-87

  4. Model Checking: Strongly-Connected Components

    1. Analysis of Symbolic SCC Hull Algorithms

      • Fabio Somenzi, Kavita Ravi, Roderick Bloem
      Pages 88-105

    2. Sharp Disjunctive Decomposition for Language Emptiness Checking

      • Chao Wang, Gary D. Hachtel
      Pages 106-122

  5. Microprocessor Specification and Verification

    1. Relating Multi-step and Single-Step Microprocessor Correctness Statements

      • Mark D. Aagaard, Nancy A. Day, Meng Lou
      Pages 123-141

    2. Modeling and Verification of Out-of-Order Microprocessors in UCLID

      • Shuvendu K. Lahiri, Sanjit A. Seshia, Randal E. Bryant
      Pages 142-159

  6. Decision Procedures

    1. On Solving Presburger and Linear Arithmetic with SAT

      • Ofer Strichman
      Pages 160-170

    2. Deciding Presburger Arithmetic by Model Checking and Comparisons with Other Methods

      • Vijay Ganesh, Sergey Berezin, David L. Dill
      Pages 171-186

    3. Qubos: Deciding Quantified Boolean Logic Using Propositional Satisfiability Solvers

      • Abdelwaheb Ayari, David Basin
      Pages 187-201

  7. Model Checking: Reachability Analysis

    1. Exploiting Transition Locality in the Disk Based Murϕ Verifier

      • Giuseppe Della Penna, Benedetto Intrigila, Enrico Tronci, Marisa Venturini Zilli
      Pages 202-219

    2. Traversal Techniques for Concurrent Systems

      • Marc Solé, Enric Pastor
      Pages 220-237

  8. Model Checking: Fixed Points

    1. A Fixpoint Based Encoding for Bounded Model Checking

      • Alan Frisch, Daniel Sheridan, Toby Walsh
      Pages 238-255

    2. Using Edge-Valued Decision Diagrams for Symbolic Generation of Shortest Paths

      • Gianfranco Ciardo, Radu Siminiceanu
      Pages 256-273
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Other volumes

  1. Formal Methods in Computer-Aided Design

Editors and Affiliations

  • Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Canada

    Mark D. Aagaard

  • Strategic CAD Labs, Intel Corporation, Hillsboro, USA

    John W. O’Leary

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