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High Performance Computing

International Symposium, ISHPC'97, Fukuoka, Japan, November 4-6, 1997, Proceedings

  • Conference proceedings
  • © 1997

Overview

Editors:
  1. Constantine Polychronopoulos
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  2. Kazuki Joe
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  3. Keijiro Araki
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  4. Makoto Amamiya
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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 1336)

Included in the following conference series:

Conference proceedings info: ISHPC 1997.

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About this book

This book constitutes the refereed proceedings of the International Symposium on High Performance Computing, ISHPC '97, held in Fukuoka, Japan in November 1997.
The volume presents four distinguished papers and 16 revised regular papers selected from more than 40 submissions on the basis of at least three peer reviews. Also included are seven invited contributions by leading authorities and 10 selected poster presentations. The papers are organized in topical chapters on high performance systems architectures, networks, compilers, systems software, and applications in various areas.

Keywords

Table of contents (37 papers)

  1. Front Matter

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  2. The generation of optimized codes using nonzero structure analysis

    • Bret A. Marsolf, Aart J. C. Bik, Kyle A. Gallivan, Harry A. G. Wijshoff
    Pages 1-29

  3. On the importance of an end-to-end view of memory consistency in future computer systems

    • Guang R. Gao, Vivek Sarkar
    Pages 30-41

  4. High performance distributed object systems

    • Dennis Gannon
    Pages 42-50

  5. Instruction cache prefetching using multilevel branch prediction

    • Alexander V. Veidenbaum
    Pages 51-70

  6. High performance wireless computing

    • George Cybenko
    Pages 71-71

  7. High-performance computing and applications in image processing and computer vision

    • Hamid R. Arabnia
    Pages 72-72

  8. Present and future of HPC technologies

    • Tadashi Watanabe
    Pages 73-74

  9. Evaluation of multithreaded processors and thread-switch policies

    • Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Beng-Hong Lime, Mark S. Squillante, C. Eric Wu
    Pages 75-90

  10. A multithreaded implementation concept of prolog on Datarol-II machine

    • Peter Kacsuk, Makoto Amamiya
    Pages 91-106

  11. Thread Synchronization Unit (TSU): A building block for high performance computers

    • Paraskevas Evripidou
    Pages 107-118

  12. Data dependence path reduction with tunneling load instructions

    • Toshinori Sato
    Pages 119-130

  13. Performance estimation of embedded software with pipeline and cache hazard modeling

    • Norbert Imlig, Akihiro Tsutsui
    Pages 131-142

  14. An implementation and evaluation of a distributed shared-memory system on workstation clusters using fast serial links

    • Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda
    Pages 143-158

  15. Designing and optimizing 3-connectivity communication networks using a distributed genetic algorithm

    • Jianhua Ma, Runhe Huang, Eiju Tsuboi
    Pages 159-170

  16. Adaptive routing on the Recursive Diagonal Torus

    • A. Funahashi, T. Hanawa, T. Kudoh, H. Amano
    Pages 171-182

  17. Achieving multi-level parallelization

    • Carrie J. Brownhill, Alexandru Nicolau, Steve Novack, Constantine D. Polychronopoulos
    Pages 183-194

  18. A technique to eliminate redundant inter-processor communication on parallelizing compiler TINPAR

    • Atsushi Kubota, Shogo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima et al.
    Pages 195-204

  19. An automatic vectorizing/parallelizing Pascal compiler V-Pascal ver. 3

    • Tetsutaro Uehara, Yoshitoshi Kunieda, Takao Tsuda
    Pages 205-216

  20. An algorithm for automatic detection of loop indices for communication overlapping

    • Kazuaki Ishizaki, Hideaki Komatsu, Toshio Nakatani
    Pages 217-230
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