Abstract
This paper presents the design and evaluation of a cache coherence adapter for the cache-coherent non-uniform memory access multiprocessor system in which symmetric multiprocessor (SMP) nodes are interconnected via Xcent-Net. The SMP node is a 4-way symmetric multiprocessor subsystem based on the Intel Xeon processors, and Xcent-Net is a dual, adaptive-routed, virtual cut-through multistage interconnection network composed of hierarchical crossbar routers. The cache coherence adapter contains a directory and a remote access cache to support the directory-based cache coherence protocol customized for the SMP nodes on Xcent-Net. For any cache design, cache size and cache line size are crucial design parameters in terms of performance and implementation, and thus they are extensively evaluated. According to the simulation results, it is shown that a 128-Mbyte remote access cache with 64-byte lines is the best choice, where the average data access latency is 9.4 μs and the effective bandwidth is 6.8 Mbytes/s per node.
This study was supported in part by research funds from Chosun University, 2003.
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Moh, S., Shim, JH., Lee, YD., Lee, JA., Cho, BJ. (2003). Design and Evaluation of a Cache Coherence Adapter for the SMP Nodes Interconnected via Xcent-Net. In: Yazıcı, A., Şener, C. (eds) Computer and Information Sciences - ISCIS 2003. ISCIS 2003. Lecture Notes in Computer Science, vol 2869. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39737-3_113
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DOI: https://doi.org/10.1007/978-3-540-39737-3_113
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