Abstract
This paper deals with the optimized implementation of high performance quadrature mixers for transmission. This work examines the most relevant architectures that may be used on FPGAs such as memory compression techniques and the CORDIC algorithm. Each technique is optimized for Virtex FPGAs in terms of area and throughput using relationally placed macros. In order to exploit the high-speed capabilities of these devices we have evaluated several VLSI architectural transforms and arithmetic techniques and we have identified which ones are still successful on FPGAs. We have applied the results of this study to the design of mixers attaining clock rates close to 280MHz.
This work was supported by the Spanish “Ministerio de Ciencia y Tecnologia” under grant number “TIC2001-2688-C03-02” and in part by the “Universitat Politecnica de Valencia” (UPV) under the Research Funding Program. Francisco Cardells-Tormo acknowledges the support of Hewlett-Packard ICD in the preparation of his Ph.D. thesis.
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Cardells-Tormo, F., Valls-Coquillat, J. (2002). High Performance Quadrature Digital Mixers for FPGAs. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_93
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DOI: https://doi.org/10.1007/3-540-46117-5_93
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