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Automatic Estimation of Verified Floating-Point Round-Off Errors via Static Analysis

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Computer Safety, Reliability, and Security (SAFECOMP 2017)

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Abstract

This paper introduces a static analysis technique for computing formally verified round-off error bounds of floating-point functional expressions. The technique is based on a denotational semantics that computes a symbolic estimation of floating-point round-off errors along with a proof certificate that ensures its correctness. The symbolic estimation can be evaluated on concrete inputs using rigorous enclosure methods to produce formally verified numerical error bounds. The proposed technique is implemented in the prototype research tool PRECiSA (Program Round-off Error Certifier via Static Analysis) and used in the verification of floating-point programs of interest to NASA.

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Notes

  1. 1.

    https://github.com/nasa/PRECiSA.

  2. 2.

    http://precisa.nianet.org.

  3. 3.

    https://shemesh.larc.nasa.gov/fm/ftp/larc/PVS-library.

  4. 4.

    Times for PRECiSA do not include type-checking of the PVS formalization, which takes approximately 4 min. However, this type-checking only occurs once at the beginning of the same PVS session used to compute all the bounds in Table 1.

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Acknowledgments

Research by the first two authors was supported by the National Aeronautics and Space Administration under NASA/NIA Cooperative Agreement NNL09AA00A.

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Authors and Affiliations

  1. National Institute of Aerospace, Hampton, VA, USA

    Mariano Moscato & Laura Titolo

  2. NASA Langley Research Center, Hampton, VA, USA

    Aaron Dutle & César A. Muñoz

Authors
  1. Mariano Moscato
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  2. Laura Titolo
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  3. Aaron Dutle
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  4. César A. Muñoz
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Corresponding authors

Correspondence to Mariano Moscato or Laura Titolo .

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Editors and Affiliations

  1. Fondazione Bruno Kessler, Trento, Italy

    Stefano Tonetta

  2. AIT Austrian Institute of Technology, Vienna, Austria

    Erwin Schoitsch

  3. Thales Deutschland GmbH, Ditzingen, Germany

    Friedemann Bitsch

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Moscato, M., Titolo, L., Dutle, A., Muñoz, C.A. (2017). Automatic Estimation of Verified Floating-Point Round-Off Errors via Static Analysis. In: Tonetta, S., Schoitsch, E., Bitsch, F. (eds) Computer Safety, Reliability, and Security. SAFECOMP 2017. Lecture Notes in Computer Science(), vol 10488. Springer, Cham. https://doi.org/10.1007/978-3-319-66266-4_14

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  • DOI: https://doi.org/10.1007/978-3-319-66266-4_14

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