Abstract
There are many articles and patents on the masking of logic gates. However, the existing publications assume that a masked logic gate switches its output no more than once per clock cycle. Unfortunately, this assumption usually does not hold true in practice.
In this article, we show that glitches occurring in circuits of masked gates make these circuits susceptible to classical first-order DPA attacks. Besides a thorough theoretical analysis of the DPA-resistance of masked gates in the presence of glitches, we also provide simulation results that confirm the theoretical elaborations. Glitches occur in every CMOS circuit. Consequently, the currently known masking schemes for CMOS gates do not prevent DPA attacks.
This work has been supported by the Austrian Science Fund (FWF Project Number P16110-N04) and by the European Commission under the Sixth Framework Programme (Project SCARD, Contract Number IST-2002-507270).
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Mangard, S., Popp, T., Gammel, B.M. (2005). Side-Channel Leakage of Masked CMOS Gates. In: Menezes, A. (eds) Topics in Cryptology – CT-RSA 2005. CT-RSA 2005. Lecture Notes in Computer Science, vol 3376. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30574-3_24
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DOI: https://doi.org/10.1007/978-3-540-30574-3_24
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