Abstract
We present a novel method for verifying the equivalence of two Boolean functions. Each function is hashed to an integer code by assigning random integer values to the input variables and evaluating an integer-valued transformation of the original function. The hash codes for two equivalent functions are always equal. Thus the equivalence of two functions can be verified with a very low probability of error, which arises from unlikely “collisions” between inequivalent functions. An upper bound, ∈, on the probability of error is known a priori. The bound can be decreased exponentially by making multiple runs. Results indicate significant time and space advantages for this method over techniques that represent each function as a single OBDD. Some functions known to require space (and time) exponential in the number of input variables for these techniques require only polynomial resources using our method. Experimental results indicate that probabilistic verification can provide an attractive alternative for verifying functions too large to be handled using these OBDD-based techniques.
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References
S.B.Akers. Binary decision diagrams. IEEE Transactions on Computers, C-27:509–516 (June 1978).
C.L. Berman. Circuit width, register allocation, and reduced function graphs. IBM Research Report, RC 14129 (October 1988).
C.L. Berman and L. Trevillyan. Functional comparison of logic designs for VLSI chips. IBM Research Report, RC 14137 (October 1988).
M.Blum, A.K.Chandra, and M.N.Wegman. Equivalence of free Boolean graphs can be decided probabilistically in polynomial time. Information Processing Letters, 10:80–82 (March 1980).
K.S. Brace, R.L. Rudell, and R.E. Bryant. Efficient implementation of a BDD package. 27th Design Automation Conference, pp. 40–45.
F. Brglez and H. Fujiwara. A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN. IEEE International Symposium on Circuits and Systems, June 1985, pp. 695–698.
R.E.Bryant. Graph based algorithms for Boolean function representation. IEEE Transactions on Computers, C-35:677–690 (August 1986).
R.E.Bryant. On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication. IEEE Transactions on Computers, C-40:206–213 (February 1991).
J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill. Sequential circuit verification using symbolic model checking. 27th Design Automation Conference, 1990, pp. 46–51.
P.Camurati and P.Prinetto. Formal verification of hardware correctness: Introduction and survey of current procedure. IEEE Computer, 21:8–19 (July 1988).
E. Cerny and C. Mauras. Tautology checking using cross-controllability and cross-observability relations. ICCAD, 1990 pp. 34–37.
L.Fortune, J.Hopcroft, and E.M.Schmidt. The complexity of equivalence and containment for free single variable program schemes. Lecture Notes in Computer Science 62: 227–240, Goos, Hartmanis, Ausiello, and Baum (eds.), Springer-Verlag, New York, 1978.
M. Fujita, H. Fujisawa, and N. Kawato. Evaluation and improvements of Boolean comparison method based on binary decision diagrams. ICCAD, 1988, pp. 2–5.
J. Jain, J. Bitner, J. Abraham, and D. Fussell. Functional partitioning for verification and related problems. Brown/MIT VLSI Conference, March 1992, pp. 210–226.
S.W. Jeong, B. Plessier, G. Hachtel, and F. Somenzi. Extended BDDs: Trading off canonicity for structure in verification algorithms. ICCAD, 1991, pp. 464–467.
R. Kapur. Personal communication, September 1991.
K. Karplus. Using if-then-else dag's for multi-level minimization. Decennial Caltech Conference on VLSI, May 1989.
C.Y.Lee. Representation of switching circuits by binary-decision programs. Bell Systems Technology Journal, 38:985–999 (1959).
T.Lengauer and R.Tarjan. A fast algorithm for finding dominators in a flowgraph. ACM Transactions on Programming Languages, 1:121–141 (July 1979).
J.C. Madre and J.P. Billon. Proving circuit correctness using formal comparison between expected and extracted behavior. 25th Design Automation Conference, 1988, pp. 205–210.
S. Malik, A. Wang, R.K. Brayton, and A. Sangiovanni-Vincentelli. Logic verification using binary decision diagrams in a logic synthesis environment. ICCAD, 1988, pp. 6–9.
B.M.E.Moret. Decision trees and diagrams. Computing Surveys, 14:593–623 (December 1982).
K.P.Parker and E.J.McCluskey. Correspondence: Probabilistic treatment of general combinational networks. IEEE Transactions on Computer, C-24:668–670 (June 1975).
R.W.Payne. Reticulation and other methods for reducing the size of printed diagnostic keys. Journal of General Microbiology, 98:595–597 (1977).
D.E. Ross. Personal communication, March 1991.
D.E.Rumelhart, J.L.McClelland, et. al. Parallel distributed processing. The MIT Press, 1:423–443 (1986).
S.K.Kumar and M.A.Breuer. Probabilistic aspects of Boolean switching functions via a new transform. Journal of ACM, 28:502–520 (July 1981).
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Jain, J., Abraham, J.A., Bitner, J. et al. Probabilistic verification of Boolean functions. Form Method Syst Des 1, 61–115 (1992). https://doi.org/10.1007/BF00464357
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DOI: https://doi.org/10.1007/BF00464357