Abstract
This paper studies the relative efficiency of variations of a tableau method for Boolean circuit satisfiability checking. The considered method is a nonclausal generalisation of the Davis–Putnam–Logemann–Loveland (DPLL) procedure to Boolean circuits. The variations are obtained by restricting the use of the cut (splitting) rule in several natural ways. It is shown that the more restricted variations cannot polynomially simulate the less restricted ones. For each pair of methods T, T′, an infinite family \(\{\mathcal{C}_{n}\}\) of circuits is devised for which T has polynomial size proofs while in T′ the minimal proofs are of exponential size w.r.t. n, implying exponential separation of T and T′ w.r.t. n. The results also apply to DPLL for formulas in conjunctive normal form obtained from Boolean circuits by using Tseitin’s translation. Thus DPLL with the considered cut restrictions, such as allowing splitting only on the variables corresponding to the input gates, cannot polynomially simulate DPLL with unrestricted splitting.
Similar content being viewed by others
Explore related subjects
Discover the latest articles, news and stories from top researchers in related subjects.References
P. Beame, R. Karp, T. Pitassi and M. Saks, The efficiency of resolution and Davis–Putnam procedures, SIAM Journal on Computing 31(4) (2002) 1048–1075.
P. Beame and T. Pitassi, Propositional proof complexity: Past, present, and future, Bulletin of the European Association for Theoretical Computer Science 65 (1998) 66–89.
A. Biere and W. Kunz, SAT and ATPG: Boolean engines for formal hardware verification, in: Proc. of the 20th IEEE/ACM International Conference on Computer Aided Design (2002) pp. 782–785.
P. Bjesse, T. Leonard and A. Mokkedem, Finding bugs in an alpha microprocessor using satisfiability solvers, in: Proc. of the 13th International Conference of Computer-Aided Verification, Lecture Notes in Computer Science, Vol. 2102 (Springer, New York, 2001) pp. 454–464.
E. Clarke, A. Biere, R. Raimi and Y. Zhu, Bounded model checking using satisfiability solving, Formal Methods in System Design 19(1) (2001) 7–34.
M. D’Agostino, D.M. Gabbay, R. Hähnle and J. Posegga, eds., Handbook of Tableau Methods (Kluwer Academic, Dordrecht, 1999).
M. D’Agostino and M. Mondadori, The taming of the cut: Classical refutations with analytic cut, Journal of Logic and Computation 4(3) (1994) 285–319.
E. Dantsin, A. Goerdt, E.A. Hirsch, R. Kannan, J. Kleinberg, C. Papadimitriou, P. Raghavan and U. Schöning, A deterministic (2−2/(k+1))n algorithm for k-SAT based on local search, Theoretical Computer Science 289(1) (2002) 69–83.
M. Davis, G. Logemann and D. Loveland, A machine program for theorem proving, Communications of the ACM 5(7) (1962) 394–397.
M. Davis and H. Putnam, A computing procedure for quantification theory, Journal of the ACM 7(3) (1960) 201–215.
M. Ganai, L. Zhang, P. Ashar, A. Gupta and S. Malik, Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver, in: Proc. of the 39th Conference on Design Automation (2002) pp. 747–750.
E. Giunchiglia, A. Massarotto and R. Sebastiani, Act, and the rest will follow: Exploiting determinism in planning as satisfiability, in: Proc. of the 15th National Conference on Artificial Intelligence and of the 10th Conference on Innovative Applications of Artificial Intelligence (1998) pp. 948–953.
E. Giunchiglia and R. Sebastiani, Applying the Davis–Putnam procedure to non-clausal formulas, in: Proc. of the Italian National Conference on Artificial Intelligence (2000) pp. 84–94.
J. Gu, P.W. Purdom, J. Franco and B.W. Wah, Algorithms for the satisfiability (SAT) problem: A survey, in: Satisfiability Problem: Theory and Applications, eds. D. Du, J. Gu and P.M. Pardalos, Discrete Mathematics and Theoretical Computer Science, Vol. 35 (Amer. Math. Soc, Providence, RI, 1997) pp. 19–152.
A. Haken, The intractability of resolution, Theoretical Computer Science 39(2/3) (1985) 297–308.
S. Jukna, Extremal Combinatorics: With Applications in Computer Science (Springer, Berlin, 2001).
T.A. Junttila, BCSat 0.3 – a satisfiability checker for Boolean circuits, Computer program (2001), available at http://www.tcs.hut.fi/Software/.
T.A. Junttila and I. Niemelä, Towards an efficient tableau method for Boolean circuit satisfiability checking, in: Computational Logic – CL 2000; First International Conference, Lecture Notes in Artificial Intelligence, Vol. 1861 (Springer, Berlin, London, UK, 2000) pp. 553–567.
H. Kautz and B. Selman, Planning as satisfiability, in: Proc. of the 10th European Conference on Artificial Intelligence (1992) pp. 359–363.
H. Kautz and B. Selman, Pushing the envelope: Planning, propositional logic, and stochastic search, in: Proc. of the 13th National Conference on Artificial Intelligence (1996) pp. 1194–1201.
A. Kuehlmann, M.K. Ganai and V. Paruthi, Circuit-based Boolean reasoning, in: Proc. of the 38th Conference on Design Automation (2001) pp. 232–237.
T. Larrabee, Test pattern generation using Boolean satisfiability, IEEE Transactions on Computer-Aided Design 11(1) (1992) 6–22.
J.P. Marques-Silva and L.G. e Silva, Solving satisfiability in combinational circuits, IEEE Design & Test of Computers 20(4) (2003) 16–21.
J.P. Marques-Silva and K.A. Sakallah, GRASP: A new search algorithm for satisfiability, in: Proc.of the 1996 IEEE/ACM International Conference on Computer-Aided Design (1997) pp. 220–227.
F. Massacci, Simplification – a general constraint propagation technique for propositional and modal tableaux, in: Proc. of the International Conference on Automated Reasoning with Analytic Tableaux and Related Methods (1998) pp. 217–231.
C.H. Papadimitriou, Computational Complexity (Addison-Wesley, Reading, MA, 1994).
D.A. Plaisted and S.A. Greenbaum, A structure-preserving clause form translation, Journal of Symbolic Computation 2 (1986) 193–304.
O. Shtrichman, Tuning SAT checkers for bounded model checking, in: Computer Aided Verification – CAV 2000; 12th International Conference, Lecture Notes in Computer Science, Vol. 1855 (Springer, New York, 2000) pp. 480–494.
C. Thiffault, F. Bacchus and T. Walsh, Solving nonclausal formulas with DPLL search, in: Proc. of the 10th International Conference on Principles and Practice of Constraint Programming (2004) pp. 663–678.
G.S. Tseitin, On the complexity of derivation in propositional calculus, in: Automation of Reasoning 2: Classical Papers on Computational Logic 1967–1970, eds. J. Siekmann and G. Wrightson (Springer, Berlin, 1983) pp. 466–483.
L. Zhang, C.F. Madigan, M.W. Moskewicz and S. Malik, Efficient conflict driven learning in Boolean satisfiability solver, in: Proc. of the International Conference on Computer Aided Design (2001) pp. 279–285.
L. Zhang and S. Malik, The quest for efficient Boolean satisfiability solvers, in: Automated Deduction – CADE-18, Lecture Notes in Computer Science, Vol. 2392 (Springer, New York, 2002) pp. 295–313.
Author information
Authors and Affiliations
Corresponding author
Additional information
AMS subject classification
03B70, 03F20, 68T15, 68T20
The financial support from Academy of Finland (project #53695) is gratefully acknowledged.
Tommi Junttila: This work was partially done while visiting ITC-IRST (Trento, Italy), and has been sponsored by the CALCULEMUS! IHP-RTN EC project, contract code HPRN-CT-2000-00102.
Rights and permissions
About this article
Cite this article
Järvisalo, M., Junttila, T. & Niemelä, I. Unrestricted vs restricted cut in a tableau method for Boolean circuits. Ann Math Artif Intell 44, 373–399 (2005). https://doi.org/10.1007/s10472-005-7034-1
Issue Date:
DOI: https://doi.org/10.1007/s10472-005-7034-1