2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2019
As IC process geometries scaled down to the Deep Sub Micron territory, industry's face severe... more As IC process geometries scaled down to the Deep Sub Micron territory, industry's face severe challenges of Timing, Run time, Congestion, QOR, Yield & manufacturing limitations. In this paper, mostly discuss on how macro placing in floorplan affect Timing, Congestion, QOR, DRC's of every stage in the design flow. Two test cases are considered to compare their congestion, utilization ratio, QOR, DRC's and finding out which macro placings is efficient for design requirement.
Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in ... more Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in 45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high threshold voltage (Vt) cell to reduce power dissipation. A 10-bit SAR ADC is designed and compared with the low resolution SAR ADC and normal threshold voltage (Vt) ADC with respect to power and delay. The results show that high Vt SAR ADC saves power upto 67% as compared to low Vt SAR ADC without any penalty of delay. Other performance metrics studied are the Effective Number of Bits (ENOB) and Signal to Noise Ratio (SNR), Signal to Noise and Distortion Ratio and Spurious Free Dynamic ratio.
2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2019
As IC process geometries scaled down to the Deep Sub Micron territory, industry's face severe... more As IC process geometries scaled down to the Deep Sub Micron territory, industry's face severe challenges of Timing, Run time, Congestion, QOR, Yield & manufacturing limitations. In this paper, mostly discuss on how macro placing in floorplan affect Timing, Congestion, QOR, DRC's of every stage in the design flow. Two test cases are considered to compare their congestion, utilization ratio, QOR, DRC's and finding out which macro placings is efficient for design requirement.
Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in ... more Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in 45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high threshold voltage (Vt) cell to reduce power dissipation. A 10-bit SAR ADC is designed and compared with the low resolution SAR ADC and normal threshold voltage (Vt) ADC with respect to power and delay. The results show that high Vt SAR ADC saves power upto 67% as compared to low Vt SAR ADC without any penalty of delay. Other performance metrics studied are the Effective Number of Bits (ENOB) and Signal to Noise Ratio (SNR), Signal to Noise and Distortion Ratio and Spurious Free Dynamic ratio.
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