2019 32nd IEEE International System-on-Chip Conference (SOCC)
Hardware Trojans are intentional addition of malicious logic into a normal circuit which is widel... more Hardware Trojans are intentional addition of malicious logic into a normal circuit which is widely regarded as one of the biggest concerns for IC industry due to the presence of a global supply chain. Being very small in size, Trojans remain dormant during manufacturing tests and only gets activated during operational mode for a rare input signal combination. Existing stuck-at-fault testing methods are insufficient for Trojan detection. In this context, a methodology to produce test vector is proposed in this work which generates rare signals inside a circuit. The proposed work uses transition probability to find rare activity nets. A set of test vectors are generated based on the impact of primary inputs on rare nets to stimulate rare signals across the netlist. The effects of final test vectors are verified with ISCAS-85 benchmark circuits and also compared with the performance of random vectors. Simulation result advocates the significance of the proposed test vectors in terms of rare net excitation.
2019 32nd IEEE International System-on-Chip Conference (SOCC), 2019
Field Programmable Gate Array (FPGA) has become an attractive platform for faster growth of the I... more Field Programmable Gate Array (FPGA) has become an attractive platform for faster growth of the Internet of Things (IoT). However, like other technologies, FPGA needs resilience against various threats. In addition, the un-monitored environment makes IoT devices more vulnerable. In this context, Physically Unclonable Function (PUF) can provide a low-cost and unique security solution over the costly conventional cryptographic system. Although Arbiter PUF (APUF) is the most suitable PUF variant for IoT, implementing a high-quality APUF on FPGA has been proved to be challenging. To date, programmable delay logic (PDL) is the widely adopted primitive to design APUF on FPGA. However, the implementation of PDL based APUF demands hard-macro feature of CAD tool which limits flexibility of the design. Also, such designs require fine-tuning to achieve PUF characteristics. This paper introduces a new switching structure named path changing switch (PCS) which is easily implementable on FPGA, and this PCS is used here to design APUF instead of the PDL. Further, the directed routing constraint is used to implement an exemplary APUF which possess better flexibility. Also, a new structure of the enable logic and manual routing is used to reduce the delay-bias. Finally, the design has been implemented over 15 different Spartan 3E FPGA boards. Experimental results show that the proposed design outperforms the PDL based APUFs in terms of PUF quality metrics without using additional fine-tuning. Also, the implemented design shows significant tolerance against temperature variations.
Journal of Computational and Theoretical Nanoscience, 2017
Reversible logic has been recognized as one of the most promising technique for the realization o... more Reversible logic has been recognized as one of the most promising technique for the realization of the quantum circuit. In this paper, a cost effective conservative, reversible binary coded decimal (BCD) adder is proposed for the quantum logic circuit. Towards the realization of BCD adder, few novel gates, such as Half-Adder/Subtraction (HAS-PP), Full-Adder/Subtraction (FAS-PP) and Overflow-detection (OD-PP) based on parity preserving logic are synthesized which incurs 7, 10 and 13 quantum cost respectively. Coupling these gates a novel tree-based methodology is proposed to implement the required BCD Adder. Also, the BCD adder design has been optimized to achieve the optimum value of quantum cost. In addition, the proposed BCD circuit is extended to n-bit adder using replica based techniques. Experimental result establishes the novelty of the proposed logic, which outperforms the conventional circuits in terms of logic synthesis and testability. The limitation of detecting the missing gate and missing control point of the quantum circuit of overflow detection is finally tackled this work by the proposed OD-PP with the application of the minimum test vector. In addition, reversible circuits of control inputs based testable master-slave D-FF is intended. The noted work on the testable sequential circuit presented here is to develop circuit using minimum test vectors and can find diverse application in the testing paradigm.
ABSTRACT Quantum-dot Cellular Automata (QCA) technology is considered as the alternative to state... more ABSTRACT Quantum-dot Cellular Automata (QCA) technology is considered as the alternative to state-of-the-art CMOS due to its extra low-power, extremely dense and high speed structures at nano-scale. This paper proposes a novel design of 2:1 multiplexer in QCA, targeting better area efficiency and reduced input to output delay.
2019 32nd IEEE International System-on-Chip Conference (SOCC)
Hardware Trojans are intentional addition of malicious logic into a normal circuit which is widel... more Hardware Trojans are intentional addition of malicious logic into a normal circuit which is widely regarded as one of the biggest concerns for IC industry due to the presence of a global supply chain. Being very small in size, Trojans remain dormant during manufacturing tests and only gets activated during operational mode for a rare input signal combination. Existing stuck-at-fault testing methods are insufficient for Trojan detection. In this context, a methodology to produce test vector is proposed in this work which generates rare signals inside a circuit. The proposed work uses transition probability to find rare activity nets. A set of test vectors are generated based on the impact of primary inputs on rare nets to stimulate rare signals across the netlist. The effects of final test vectors are verified with ISCAS-85 benchmark circuits and also compared with the performance of random vectors. Simulation result advocates the significance of the proposed test vectors in terms of rare net excitation.
2019 32nd IEEE International System-on-Chip Conference (SOCC), 2019
Field Programmable Gate Array (FPGA) has become an attractive platform for faster growth of the I... more Field Programmable Gate Array (FPGA) has become an attractive platform for faster growth of the Internet of Things (IoT). However, like other technologies, FPGA needs resilience against various threats. In addition, the un-monitored environment makes IoT devices more vulnerable. In this context, Physically Unclonable Function (PUF) can provide a low-cost and unique security solution over the costly conventional cryptographic system. Although Arbiter PUF (APUF) is the most suitable PUF variant for IoT, implementing a high-quality APUF on FPGA has been proved to be challenging. To date, programmable delay logic (PDL) is the widely adopted primitive to design APUF on FPGA. However, the implementation of PDL based APUF demands hard-macro feature of CAD tool which limits flexibility of the design. Also, such designs require fine-tuning to achieve PUF characteristics. This paper introduces a new switching structure named path changing switch (PCS) which is easily implementable on FPGA, and this PCS is used here to design APUF instead of the PDL. Further, the directed routing constraint is used to implement an exemplary APUF which possess better flexibility. Also, a new structure of the enable logic and manual routing is used to reduce the delay-bias. Finally, the design has been implemented over 15 different Spartan 3E FPGA boards. Experimental results show that the proposed design outperforms the PDL based APUFs in terms of PUF quality metrics without using additional fine-tuning. Also, the implemented design shows significant tolerance against temperature variations.
Journal of Computational and Theoretical Nanoscience, 2017
Reversible logic has been recognized as one of the most promising technique for the realization o... more Reversible logic has been recognized as one of the most promising technique for the realization of the quantum circuit. In this paper, a cost effective conservative, reversible binary coded decimal (BCD) adder is proposed for the quantum logic circuit. Towards the realization of BCD adder, few novel gates, such as Half-Adder/Subtraction (HAS-PP), Full-Adder/Subtraction (FAS-PP) and Overflow-detection (OD-PP) based on parity preserving logic are synthesized which incurs 7, 10 and 13 quantum cost respectively. Coupling these gates a novel tree-based methodology is proposed to implement the required BCD Adder. Also, the BCD adder design has been optimized to achieve the optimum value of quantum cost. In addition, the proposed BCD circuit is extended to n-bit adder using replica based techniques. Experimental result establishes the novelty of the proposed logic, which outperforms the conventional circuits in terms of logic synthesis and testability. The limitation of detecting the missing gate and missing control point of the quantum circuit of overflow detection is finally tackled this work by the proposed OD-PP with the application of the minimum test vector. In addition, reversible circuits of control inputs based testable master-slave D-FF is intended. The noted work on the testable sequential circuit presented here is to develop circuit using minimum test vectors and can find diverse application in the testing paradigm.
ABSTRACT Quantum-dot Cellular Automata (QCA) technology is considered as the alternative to state... more ABSTRACT Quantum-dot Cellular Automata (QCA) technology is considered as the alternative to state-of-the-art CMOS due to its extra low-power, extremely dense and high speed structures at nano-scale. This paper proposes a novel design of 2:1 multiplexer in QCA, targeting better area efficiency and reduced input to output delay.
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