32nd Reconfigurable Architectures Workshop
Official website: raw.necst.it
June 3rd-4th 2025. Milano, Italy

The 32nd Reconfigurable Architectures Workshop (RAW 2025) will be held in Milano, Italy on june 3rd and 4th 2025. RAW 2025 is associated with the 39th Annual IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2025) and is sponsored by the IEEE Computer Society and the Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

RAW Program

★ Indicates best paper candidate
★ Indicates best paper/poster winner
Location for all sessions: Building 3

June 3rd
PDT	Opening Session
8.30-8.45	Registration
9.00-9.15	Opening
9.15-10.30	Keynote Lana Josipovic: TBD
10.30-11.00	Coffee Break
	Session 1: Fantastic Machine Learning Systems and Where To Find Them Chair: Prof. Hayden Kwok-Hay So, University of Hong Kong
11.10-11.25	RAW-02	Muhammad Ali Farooq, Suhaib A Fahmy, Abid Rafique, Aman Arora: High Throughput Low Latency Network Intrusion Detection on FPGAs: a Raw Packet Approach
11.25-11.50	RAW-04	Brindusa Mihaela Damian-Kosterhon, Felix Kosterhon, Lucian Petrica, Andreas Koch: Improving mapping of convolutional neural networks on FPGAs through tailored macro sizes
11.50-12.00		Antonio Miele: Introduction for Poster Session and PhD Forum
12.15-12.16	RAW-14	Rodrigo Olmos, Andres Otero: An FPGA-Accelerated Framework for Optimizing Decision Tree Ensembles in Supervised Learning (Poster)
12.16-12.17	RAW-15	Yoshiki Yamaguchi, Tomoya Yokono: Accelerating CRS Format Conversion for Sparse Matrix Computation with an FPGA (Poster)
12.17-12.18	RAW-09	Eleonora Cabai, Giuseppe Sorrentino, Davide Conficconi, Marco Domenico Santambrogio: A Hardware/Software Co-Design Approach for Versal-Based K-means Acceleration (Poster)
12.18-12.19	RAW-10	Davide Ettori, Giuseppe Sorrentino, Federico Mansutti, Marco Domenico Santambrogio, Davide Conficconi: Towards a Methodology to Leverage Alveo Versal System Usability And Parallelization (Poster)
12.19-12.20	RAW-05	Aya Jendoubi, Jean-Christophe Prévotet, Philippe Tanguy, Pascal Cotret: Security of Dynamically Reconfigurable RISC-V Systems: I/O Attack Focus (Poster)
12.30-14.00	Poster Session & PhD Forum & Lunch break
Computer Architectures and Beyond
14.00-14.25	RAW-11	Matthias Nickel, Rohan Krishna Vijayaraghavan, Ahmed Kamaleldin, Diana Göhringer: A RISC-V Coprocessor for Seamless Integration of Stream-Based Accelerators ★
14.25-14.50	RAW-13	Martin Langhammer, Kim Bozman, Gregg Baeckler: A 950MHz SIMT Soft Processor★
14.50-15.15	RAW-16	Luis Waucquez, Alfonso Rodríguez: Reconfigurable Processor-Centric Accelerators for Safety-Critical Applications ★
15.35-16.00		Behzad Salami: FPGA-Driven Pre-Silicon Emulation and Design Flow Acceleration for RISC-V Architectures (Invited)
16.00-16.30		Coffee break
Special Session on Efficient Reconfigurable Systems and Efficient AI
16.30-16.55	RAW-12	Noemi D’Abbondanza, Stylianos Tzelepis, Nicolo Ghielmetti, Ioannis Kakogeorgiou, Vanya Buchova, Konstantinos Karantzalos, Katerina Kikaki, Nicolas-Marcel Lemoine, Maurizio Pierini, Sioni Summers, Simon Vellas, Francois de Vieilleville, Boyan-Nikola Zafirov: Edge SpAIce: Deep Learning Deployment Pipeline for Onboard Data Reduction on Satellite FPGAs (Invited)
16.55-17.20		Shulin Zeng: Enabling FPGAs for Efficient Generative AI Inference (Invited)
17.20-17.45		Fabrizio Ferrandi, Serena Curzel: HERMES: Qualification of High-performance Programmable Microprocessor and Development of Software Ecosystem (Invited)
17.45-18.00		Panel Session from Invited Speakers

June 4th
8.30-9.00	Registration
9.00-10.15	Keynote Suhaib A Fahmy: Boosting FPGA Accelerator Performance with Primitive-Aware Design
10.30-11.00	Coffee break
Correcting Errors in the Wild: from Digital Design to Quantum Computing
11.00-11.25	RAW-01	Yngve Hafting, Alexander Wold: Testbench analysis using non-invasive fault injection
11.25-11.50		Marco Venere, Federico Valentino: TBA, Quantum Computing (Invited)
11.50-12.15		Kentaro Sano: Quantum error correction algorithm and FPGA-based backend system for Fault-tolerant quantum computers (Invited)
12.15-12.30	Panel Session from Invited Speakers
12.30-14.00	Lunch break
Special Session on European Excellence for Emerging Technologies
14.00-14.20		Catalin Ciobanu: Invited Talk from ISOLDE European Project (Invited)
14.20-14.40		Jurgen Becker: TBA (Invited)
14.40-15.00		Dirk Strootbandt: The European Chips Competence Center in Flanders (Invited)
15.00-15.20	Panel Session
15.20-15.40	Awards and Closing Ceremony
16.00-16.30	Coffee break
16.30-18.00	Forward-Looking Panel: "Revolutionizing Parallel & Distributed Computing: The Quantum, LLM Systems, and AI-Driven Future of HPC" by IPDPS
18.00-19.30	Welcome Reception TCPP Welcome Reception by IPDPS

Keynotes

Tuesday Keynote: TBD

Abstract: TBD

Speaker Bio: TBD

Wednesday Keynote: Boosting FPGA Accelerator Performance with Primitive-Aware Design

Abstract: We expect FPGAs to perform poorly compared to ASICs; no doubt their flexibility and reconfigurability come at a significant cost in terms of performance and energy. However, are we really getting the most out of today’s FPGAs? With fabrics that can support frequencies of up to 800MHz or more, why do we find designs that run at a quarter of that frequency acceptable? In this talk, we will zoom into the DSP blocks on modern FPGAs: marvels of capability and flexibility, that can drive a significant boost in performance, when suitably employed. We will show how design that considers these primitives at its core can achieve significant performance improvements over those agnostic to the FPGA architecture. We will see this impact across soft processors, overlay architectures, and large integer multipliers, showing that a methodology that is primitive-aware can lead to significant frequency improvements. We will finally ask how we can build better tools to leverage these capabilities to boost the performance of FPGA accelerators.

Speaker Bio: Suhaib Fahmy is Associate Professor of Computer Science and Principal Investigator of the Accelerated Connected Computing Lab (ACCL) at KAUST, Saudi Arabia. His research explores hardware acceleration and integration of these accelerators within wider computing infrastructure. He graduated from from Imperial College London with an MEng in 2003 and PhD in 2008. He completed a Postdoctoral Research Fellowship at Trinity College Dublin in collaboration with Xilinx Research Labs, Ireland, before joining Nanyang Technological University, Singapore as Assistant Professor in 2009. He was Associate Professor, Reader then Full Professor of Computer Engineering at the University of Warwick from 2015, from where he is currently on leave. Dr Fahmy received Best Paper Awards at FPT 2012, ACM TODAES 2019, IEEE HPEC 2021, and the Community Award at FPL 2016 and 2024. He received IBM Faculty Awards in 2013 and 2017 and was a Turing Fellow at the Alan Turing Institute from 2017 to 2021. He sits on the ACM Technical Committee on FPGAs and is a Chartered Engineer and Fellow of the IET, as well as a Senior Member of the ACM and IEEE.

Presentation and Poster Logistics

Please check the program to align your travel plans. If there is any risk that you might have travel complications, please let the Program Chair/Workshop Chair know ASAP!
Regular paper sessions:

• Each full paper has a 25mins slot: 1.5min transition and intro + 20min talk + 3.5min Q/A.
• Each short paper has a 10mins slot: 1.5min transition and intro + 8.5min talk, no Q/A. Each short paper will have to present a poster as well.
• Watch for an email from your session chair and send them a short bio for introduction.
• There will be a conference laptop for presentations. Please work with your session chair to upload and test your slides before your session starts. If you prefer to using your own laptop, please inform your session chair beforehand.
• Best paper award: A selection committee will attend the presentation of all three best paper candidates, and announce the decision during the workshop closing and award ceremony. There will be a $500 cash award for the final best paper.

Panel-like special sessions:

• 5min transition and intro
• 1 hour pitch presentation: each speaker has about 15min, with 4 speakers in a session
• 45min panel discussion, Q/A from audience

Posters:

• RAW will provide easels with double-sided 4x8 feet cork boards, and push pins/clips for the posters. It’s recommended to print your poster no larger than an A0 paper size (841 x 1189 mm or 33.1 x 46.8 in).
• It’s also recommended to print your poster beforehand and bring it to the workshop.
• Here are some best practices on how to prepare a poster.
• Best poster award: Each attendee will be given a ballot and vote for the best poster after they visit all the posters. The final best poster will be announced during the workshop closing and award ceremony. There will be a $500 cash award for the final best poster.

Topics of interest

Paper Submission

Submission Rounds

This year RAW will have a single submission round at the end of January.

TRETS special issue on RAW 2025

After the experiments of RAW2024, we will continue to push for a journal special issue. For RAW 2025, we are collaborating with ACM TRETS to organize a journal special issue. We will invite top papers from the RAW 2025 program to extend their work and submit to the ACM TRETS special issue on RAW 2025.

Submission Rules

All manuscripts will be reviewed by at least three members of the program committee, with a single-blind review process. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. There are two types of manuscripts: 1) full papers (up to 6 pages) and 2) short papers (up to 4 pages). Both manuscripts should follow the IEEE conference style: single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages. The page limits exclude references and both manuscripts can include up to 2 pages of references. A conformant LaTeX template is available here: here. Overleaf users can find the LaTeX template here. A Microsoft Word template is available here.

Submission Link

Papers are to be submitted through Linkings. All papers must be submitted electronically in PDF format. Submitted papers should not have appeared in or be under submission for a different workshop, conference or journal. It is also expected that all accepted papers (full or short) will be presented at the workshop by one of the authors.

Reviewer Conflict Policy

During paper submission (in “Conflicts > My Conflicts”), all author(s) conflicts must be registered with all possible program committee members. Conflicts are defined as all relationships that would prevent a reviewer from objectively evaluating the submitted work. This includes, but is not limited to, having within the past 5 years, 1) co-authored a publication, or 2) shared a funding award, and 3) shared at least one institutional affiliation. Note: if a conflict is declared (or left undeclared) in an attempt to manipulate the review process, the submission may be rejected.

Publication and Journal Special Issue

IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. Proceedings of the workshops are distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference. We will also invite top papers from the workshop to extend their work and submit to the ACM TRETS special issue on RAW 2025.

Important Dates

• Submission deadline: Jan 20, 2025 Feb 3, 2025
• Decision notification: Feb 14, 2025 Feb 26, 2025
• Camera-ready: Mar 6, 2025 Mar 13, 2025
• Conference: June 3-4, 2025

All submission deadlines are 11:59 pm Anywhere on Earth (UTC -12).

RAW 2025 Awards

• Best paper: Selected after the presentation of the 3 best paper candidates.
• Best poster: Selected among all the poster presentations at RAW 2025.
• Best artifact: See the following section for more information.

Call for PhD Forum

The Reconfigurable Architectures Workshop (RAW) is pleased to announce the Ph.D Forum. The forum is an excellent opportunity for PhD students to present their research and engage with the broader reconfigurable computing community. PhD students conducting research in reconfigurable computing and related fields are invited to participate in the poster session, where they can share their work, exchange ideas, and receive feedback from experienced researchers and peers
To apply for the forum, prospective participants will be required to submit a two-page extended abstract using IEEE conference standard template. Please highlight the student and the advisor(s) in the submission

Deadline: April 28th, 2025
How: send an email with Object: “[RAW25 - PhD Forum]” to antonioDOTmieleATpolimiDOTit

Artifact Evaluation

RAW 2025 will continue the experimental Artifact Evaluation (AE) initiated in RAW 2023. Authors of accepted papers at RAW 2025 can optionally participate in the AE process to formally describe supporting materials(code, data, models, workflows, results).

Artifacts are digital objects that were created by the authors as part of the research or experiments performed with the submitted work. Examples of artifacts are:

• Software: models, source code, scripts, Makefiles, container images (like Docker files), etc.
• Hardware: Verilog, VHDL, schematics, CAD tools, flows, etc.
• Data: spreadsheets, databases, binary files, design sets, etc.

High-quality artifacts are as important as the manuscript itself. The goal of submitting artifacts promotes the availability and reproducibility of the experimental results and data such that other researchers can repeat experiments and replicate results with less effort.

Note that this submission is voluntary and will not influence the final decision regarding the papers. The goal is to help the authors validate experimental results from their accepted papers by an independent AE Committee (AEC) in a collaborative way while helping readers find articles with available (i.e., publicly accessible in an archival repository), functional (i.e., consistent, documented, and reusable), and validated (i.e., main results from the paper) artifacts.

Each submitted artifact is evaluated by at least two members of the AEC. During the process, authors and evaluators are allowed to communicate anonymously with each other to overcome technical difficulties. Ideally, we hope to see all submitted artifacts successfully pass the artifact evaluation. More details on the AE process will follow, and in the meantime check the FAQ.

Finally, we are seeking volunteers to take part in the AE Committee. If you are interested in taking part in this initiative please consider to submit your candidacy or those of your students through this form.

Organization

Workshop Chair

• Marco Domenico Santambrogio, Politecnico di MIlano, Italy

Program Co-Chairs

• Davide Conficconi, Politecnico di MIlano, Italy
• Zhenman Fang, Simon Fraser University, Canada

Steering Committee

• Juergen Becker, Karlsruhe Institute of Technology, Germany
• Viktor K. Prasanna, University of Southern California, USA
• Ramachandran Vaidyanathan, Louisiana State University, USA
• Marco Domenico Santambrogio, Politecnico di MIlano, Italy

Steering Chair

• Viktor K. Prasanna, University of Southern California, USA

Artifacts Chair

• Francesco Peverelli, Politecnico di Milano, Italy

PhD Forum Chair

• Antonio Miele, Politecnico di Milano, Italy

Publicity Co-Chairs

• Brian Veale, IBM, USA
• Christian Pilato, Politecnico di Milano, Italy

Webmaster

• Laura Ginestretti, Politecnico di Milano, Italy

Program Committee

• Jason Anderson, University of Toronto
• Aman Arora, Arizona State University
• Andrew Boutros, University of Waterloo
• Ray Cheung, University of Hong Kong
• Young-kyu Choi, Inha University
• Cătălin Bogdan Ciobanu, University of Transilvania Bra»ôov
• Davide Conficconi, Politecnico di Milano
• Emanuele Del Sozzo, Massachusetts Institute of Technology
• Zhenman Fang, Simon Fraser University
• Wenyi Feng, Ouster Inc
• Francisco Fons Lluis, Huawei Technologies
• Diana Goehringer, Technical University Dresden
• Martin C. Herbordt, Boston University
• Christian Hochberger, TU Darmstadt
• Jim Hwang, AMD
• Kazushi Kawamura, Tokyo Institute of Technology
• Ryohei Kobayashi, University of Tsukuba
• Martin Langhammer, Altera
• Sergiu Mosanu, University of Virginia, Micron Technology
• Andrés Otero, Universidad Politécnica de Madrid
• Dionisios Pnevmatikatos, National Technical University of Athens
• Mario Porrmann, Osnabrueck University
• Thomas Preußer, AMD Research
• Behzad Salami, Barcelona Supercomputing Center
• Marco Domenico Santambrogio, Politecnico di Milano
• Yukinori Sato, Toyohashi University of Technology
• Yuichiro Shibata, Nagasaki University
• Muhammad Ali Siddiqi, Lahore University of Management Sciences
• Magnus Själander, Norwegian University of Science and Technology
• Hayden HK So, University of Hong Kong
• Dimitrios Soudris, NTUA
• Ioannis Sourdis, Chalmers University of Technology
• Tomohiro Ueno, RIKEN Center for Computational Science (R-CCS)
• Ramachandran Vaidyanathan, Louisiana State University
• Zeke Wang, Zhejiang University
• Shouyi Yin, Tsinghua University
• Jincheng Yu, Tsinghua University
• Chen Zhang, Shanghai Jiao Tong University