Sara: Scaling a reconfigurable dataflow accelerator Y Zhang, N Zhang, T Zhao, M Vilim, M Shahbaz, K Olukotun 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 56 | 2021 |
Capstan: A vector RDA for sparsity A Rucker, M Vilim, T Zhao, Y Zhang, R Prabhakar, K Olukotun MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 38 | 2021 |
Approximate bitcoin mining M Vilim, H Duwe, R Kumar Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 36 | 2016 |
Gorgon: Accelerating machine learning from relational data M Vilim, A Rucker, Y Zhang, S Liu, K Olukotun 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 32 | 2020 |
Scalable interconnects for reconfigurable spatial architectures Y Zhang, A Rucker, M Vilim, R Prabhakar, W Hwang, K Olukotun Proceedings of the 46th International Symposium on Computer Architecture …, 2019 | 31 | 2019 |
Aurochs: An architecture for dataflow threads M Vilim, A Rucker, K Olukotun 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 18 | 2021 |
SARA: Scaling a Reconfigurable Dataflow Accelerator. In 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). 1041–1054 Y Zhang, N Zhang, T Zhao, M Vilim, M Shahbaz, K Olukotun IEEE, 2021 | 13 | 2021 |
Gorgon: Accelerating Machine Learning from Relational Data. In 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). 309–321 M Vilim, A Rucker, Y Zhang, S Liu, K Olukotun | 10 | 2020 |
Revet: A language and compiler for dataflow threads AC Rucker, S Sundram, C Smith, M Vilim, R Prabhakar, F Kjølstad, ... 2024 IEEE International Symposium on High-Performance Computer Architecture …, 2024 | 7 | 2024 |
Aurochs: An Architecture for Dataflow Threads. In 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). 402–415 M Vilim, A Rucker, K Olukotun IEEE, 2021 | 7 | 2021 |
Heat-based Decontamination of N95 Masks Using a Commercial Laundry Dryer YD Lensky, EA Mazenc, D Ranard, M Vilim, M Prakash, B Brooks, ... medRxiv, 2020.07. 22.20160283, 2020 | 2 | 2020 |
In-Database Machine Learning on Reconfigurable Dataflow Accelerators M Vilim Stanford University, 2021 | 1 | 2021 |
Coupling Operations on Dynamically-Sized Data Structures in Data Flow Architectures A Srivastava, M Vilim, R Prabhakar, S Rachuru, Z Zhang, M Musaddiq, ... US Patent App. 18/884,707, 2025 | | 2025 |
System for Implementing Operations Having Dynamically-Sized Data Structures on a Reconfigurable Processor. A Srivastava, M Vilim, R Prabhakar, S Rachuru, Z Zhang, M Musaddiq, ... US Patent App. 18/884,690, 2025 | | 2025 |
HANDLING DYNAMIC TENSOR LENGTHS IN A RECONFIGURABLE PROCESSOR THAT INCLUDES MULTIPLE MEMORY UNITS A Srivastava, M Vilim, R Prabhakar, S Rachuru, Z Zhang, M Musaddiq, ... US Patent App. 18/213,598, 2024 | | 2024 |
Dataflow architecture processor statically reconfigurable to perform n-dimensional affine transformation M Vilim, R Prabhakar, M Feldman, Y Zhang US Patent App. 18/095,132, 2024 | | 2024 |
Dataflow architecture processor statically reconfigurable to perform n-dimensional affine transformation in a tiled manner M Vilim, R Prabhakar, M Feldman, Y Zhang US Patent App. 18/095,128, 2024 | | 2024 |
Dataflow architecture processor statically reconfigurable to perform n-dimensional affine transformation in parallel manner by replicating copies of input image across … M Vilim, R Prabhakar, M Feldman, Y Zhang US Patent App. 18/095,134, 2024 | | 2024 |
Dataflow architecture processor statically reconfigurable to perform n-dimensional affine transformation in parallel manner by replicating copies of input image across multiple … M Vilim, R Prabhakar, M Feldman, Y Zhang US Patent App. 18/095,137, 2024 | | 2024 |
Dynamically-Sized Data Structures on Data Flow Architectures A Srivastava, M Vilim, R Prabhakar, S Rachuru, Z Zhang, M Musaddiq, ... US Patent App. 18/109,590, 2023 | | 2023 |