Practical and scalable evolution of digital circuits
AP Shanthi, R Parthasarathi - Applied Soft Computing, 2009 - Elsevier
Applied Soft Computing, 2009•Elsevier
This paper addresses the scalability problem prevalent in the evolutionary design of digital
circuits and shows that Evolvable Hardware (EHW) can indeed be considered as a viable
alternative design methodology for large and complex circuits. Despite the effort by the EHW
community to overcome the scalability problems using both direct mapped techniques and
developmental approaches, so far only small circuits have been evolved. This paper shows
that, by partitioning a digital circuit and making use of a modular developmental approach …
circuits and shows that Evolvable Hardware (EHW) can indeed be considered as a viable
alternative design methodology for large and complex circuits. Despite the effort by the EHW
community to overcome the scalability problems using both direct mapped techniques and
developmental approaches, so far only small circuits have been evolved. This paper shows
that, by partitioning a digital circuit and making use of a modular developmental approach …
This paper addresses the scalability problem prevalent in the evolutionary design of digital circuits and shows that Evolvable Hardware (EHW) can indeed be considered as a viable alternative design methodology for large and complex circuits. Despite the effort by the EHW community to overcome the scalability problems using both direct mapped techniques and developmental approaches, so far only small circuits have been evolved. This paper shows that, by partitioning a digital circuit and making use of a modular developmental approach, namely, the Modular Developmental Cartesian Genetic Programming (MDCGP) technique, it is indeed possible to evolve large circuits. As a proof of concept, a 5×5 multiplier is evolved for partition sizes of 32 and 64. It is shown that compared to the direct evolution technique, the MDCGP technique provides five times reduction in terms of evolution times, 6–56% reduction in area and improved fault tolerance. The technique is readily scalable and can be applied to even larger partition sizes, and also to sequential circuits, thus providing a promising path to evolve large and complex circuits.
Elsevier