Multithreaded processor architectures
GT Byrd, MA Holliday - Ieee Spectrum, 1995 - ieeexplore.ieee.org
Ieee Spectrum, 1995•ieeexplore.ieee.org
The authors describe how independent streams of instructions, interwoven on a single
processor, fill its otherwise idle cycles and so boost its performance. They detail how such
multithreaded architectures take the tack of hiding latency by supporting multiple concurrent
streams of execution. When a long-latency operation occurs in one of the threads, another
begins execution. In this way, useful work is performed while the time-consuming operation
is completed.<>
processor, fill its otherwise idle cycles and so boost its performance. They detail how such
multithreaded architectures take the tack of hiding latency by supporting multiple concurrent
streams of execution. When a long-latency operation occurs in one of the threads, another
begins execution. In this way, useful work is performed while the time-consuming operation
is completed.<>
The authors describe how independent streams of instructions, interwoven on a single processor, fill its otherwise idle cycles and so boost its performance. They detail how such multithreaded architectures take the tack of hiding latency by supporting multiple concurrent streams of execution. When a long-latency operation occurs in one of the threads, another begins execution. In this way, useful work is performed while the time-consuming operation is completed.< >
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