Instruction set extensions for multi-threading in LEON3
M Danek, L Kafka, L Kohout… - 13th IEEE Symposium on …, 2010 - ieeexplore.ieee.org
13th IEEE Symposium on Design and Diagnostics of Electronic …, 2010•ieeexplore.ieee.org
This paper describes instruction set extensions for a variant of multi-threading called micro-
threading for the LEON3 SPARCv8 processor. We show an architecture of the developed
processor and its key blocks-cache controller, register file, thread scheduler. The processor
has been implemented in a Xilinx Virtex2Pro FPGA. The extensions are evaluated in terms
of extra resources needed, and the overall performance of the developed processor is
evaluated on a simple DSP computation typical for embedded systems.
threading for the LEON3 SPARCv8 processor. We show an architecture of the developed
processor and its key blocks-cache controller, register file, thread scheduler. The processor
has been implemented in a Xilinx Virtex2Pro FPGA. The extensions are evaluated in terms
of extra resources needed, and the overall performance of the developed processor is
evaluated on a simple DSP computation typical for embedded systems.
This paper describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. We show an architecture of the developed processor and its key blocks - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro FPGA. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is evaluated on a simple DSP computation typical for embedded systems.
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