Design and performance analysis of dual die Pentium® 4 package
A Sarangi, M Suryakumar - 2006 IEEE Electrical Performane of …, 2006 - ieeexplore.ieee.org
A Sarangi, M Suryakumar
2006 IEEE Electrical Performane of Electronic Packaging, 2006•ieeexplore.ieee.orgThe continued growth of power consumption has presented numerous packaging
challenges for high performance processors. Even though voltage is a strong knob to reduce
power, reducing voltage also reduces the maximum operating frequency (M. Suryakumar et
al., 2006). Integrating more cores into the processor would result in better performance and
power efficiency but this requires more memory accesses, driving a need for larger cache
and high speed signaling, increasing package size and layer count. This paper discusses …
challenges for high performance processors. Even though voltage is a strong knob to reduce
power, reducing voltage also reduces the maximum operating frequency (M. Suryakumar et
al., 2006). Integrating more cores into the processor would result in better performance and
power efficiency but this requires more memory accesses, driving a need for larger cache
and high speed signaling, increasing package size and layer count. This paper discusses …
The continued growth of power consumption has presented numerous packaging challenges for high performance processors. Even though voltage is a strong knob to reduce power, reducing voltage also reduces the maximum operating frequency (M. Suryakumar et al., 2006). Integrating more cores into the processor would result in better performance and power efficiency but this requires more memory accesses, driving a need for larger cache and high speed signaling, increasing package size and layer count. This paper discusses the design strategy for power delivery and compares performance of the dual die packages through measurements
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