Demonstration of a 12 nm-half-pitch copper ultralow-k interconnect process
JS Chawla, R Chebiam, R Akolkar… - 2013 IEEE …, 2013 - ieeexplore.ieee.org
2013 IEEE International Interconnect Technology Conference-IITC, 2013•ieeexplore.ieee.org
A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer
dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer
that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical
measurements that validate functionality of the drawn structures are presented.
dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer
that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical
measurements that validate functionality of the drawn structures are presented.
A process to achieve 12 nm half-pitch interconnect structures in ultralow-k interlayer dielectric (ILD) is realized using standard 193 nm lithography. An optimized pattern transfer that minimizes unwanted distortion of ILD features is followed by copper fill. Electrical measurements that validate functionality of the drawn structures are presented.
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