Three-dimensional (3D) Thru-Silicon-Via (TSV) integration is emerging as a key enabling technology for future high performance systems. The TSV manufacturing defect rates lead to significant interconnect yield loss. For intra-die and inter-die interconnects, techniques such as via widening, via spreading and spare via insertion have been successfully used to improve the yield. However, for high fault rates these solutions are less effective and lead to unacceptable overheads. In this paper, configurable serial fault tolerant links are proposed for inter-die communication in 3D integrated systems. For high TSV fault rates, serial data transmission and signal remapping on fault-free wires are jointly used to ensure correct data transmission. After the interconnect tests, if faulty wires are detected then the link serializes data transmission such that only fault free wires are used. In the proposed link, any subset of data bits can be mapped on any subset of functional wires. Selecting a threshold serialization rate above which the link fails, enables optimal link designs that target interconnect technologies with high fault rates. The impact of inter-die configurable serial fault tolerant links on the performance and area overheads of 3D mesh networks-on-chip (3D NoC) is analyzed. The results show that for an 80% interconnect fault rate the latency degradation up to 14% and area overheads go up to 30%.