We address the design of algorithms for multicores that are oblivious to machine
parameters. We propose HM, a multicore model consisting of a parallel shared-memory
machine with hierarchical multi-level caching, and we introduce a multicore-oblivious
approach to algorithms and schedulers for HM. A multicore-oblivious algorithm is specified
with no mention of any machine parameters, such as the number of cores, number of cache
levels, cache sizes and block lengths. However, it is equipped with a small set of instructions …