The design and implementation of a first-generation CELL processor
D Pham, S Asano, M Bolliger, MN Day… - ISSCC. 2005 IEEE …, 2005 - ieeexplore.ieee.org
D Pham, S Asano, M Bolliger, MN Day, HP Hofstee, C Johns, J Kahle, A Kameyama, J Keaty…
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid …, 2005•ieeexplore.ieee.orgA CELL processor is a multi-core chip consisting of a 64b power architecture processor,
multiple streaming processors, a flexible IO interface, and a memory interface controller. This
SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of
modularity and reuse to maximize the custom circuit content and achieve a high-frequency
clock-rate.
multiple streaming processors, a flexible IO interface, and a memory interface controller. This
SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of
modularity and reuse to maximize the custom circuit content and achieve a high-frequency
clock-rate.
A CELL processor is a multi-core chip consisting of a 64b power architecture processor, multiple streaming processors, a flexible IO interface, and a memory interface controller. This SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of modularity and reuse to maximize the custom circuit content and achieve a high-frequency clock-rate.
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