[PDF][PDF] Chain: a delay-insensitive chip area interconnect
J Bainbridge, S Furber - IEEE Micro, 2002 - apt.cs.manchester.ac.uk
J Bainbridge, S Furber
IEEE Micro, 2002•apt.cs.manchester.ac.ukthe slowest stage. The key difference is that with a synchronous approach, the entire
interconnect must be operated from the same clock, or a multiple thereof, whereas the
asynchronous approach is self-regulating, operating as fast as the paths allow. The “Self-
timed circuits” sidebar (next page) gives a detailed explanation of how asynchronous circuits
work. The pipe latches in Figure 1 represent the self-timed latch stages for the one-hot links.
4 The loop between these latches can be thought of as a ring oscillator, interlocked with the …
interconnect must be operated from the same clock, or a multiple thereof, whereas the
asynchronous approach is self-regulating, operating as fast as the paths allow. The “Self-
timed circuits” sidebar (next page) gives a detailed explanation of how asynchronous circuits
work. The pipe latches in Figure 1 represent the self-timed latch stages for the one-hot links.
4 The loop between these latches can be thought of as a ring oscillator, interlocked with the …
the slowest stage. The key difference is that with a synchronous approach, the entire interconnect must be operated from the same clock, or a multiple thereof, whereas the asynchronous approach is self-regulating, operating as fast as the paths allow. The “Self-timed circuits” sidebar (next page) gives a detailed explanation of how asynchronous circuits work.
The pipe latches in Figure 1 represent the self-timed latch stages for the one-hot links. 4 The loop between these latches can be thought of as a ring oscillator, interlocked with the preceding and following stages via the Muller C-elements, with the minimum oscillation period determined by the two C-elements, the OR gate, the inverter, and the
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