The complexity of System-on-Chip (SoC) designs continues to grow as each SoC features an increasing variety of loosely coupled accelerators together with multiple processor cores. Specialized-hardware accelerators are typically designed in isolation, optimized for the algorithm they are implementing, and with limited consideration of the implications of their integration into a given SoC. However, the interaction between these accelerators and the memory hierarchy is critically important for their performance and the performance of the overall SoC. By leveraging our platform for rapid SoC prototyping, we analyze three models of coherence for loosely coupled accelerators from a system-level perspective.