Design techniques to reduce SET pulse widths in deep-submicron combinational logic
OA Amusan, LW Massengill, BL Bhuva… - … on Nuclear Science, 2007 - ieeexplore.ieee.org
IEEE Transactions on Nuclear Science, 2007•ieeexplore.ieee.org
Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection
and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET
pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on
the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact
layout for SET RHBD in combinational logic.
and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET
pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on
the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact
layout for SET RHBD in combinational logic.
Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact layout for SET RHBD in combinational logic.
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