[PDF][PDF] A heuristic method for FPGA technology mapping based on the edge visibility
NS Woo - Proceedings of the 28th ACM/IEEE Design Automation …, 1991 - dl.acm.org
NS Woo
Proceedings of the 28th ACM/IEEE Design Automation Conference, 1991•dl.acm.orgWe present an efficient technology mapping method for lookup table-based FPGA
architectures. We first introduce lhc notion of edge visibility. Wc then formulate lhc problem of
finding the area-optimal technology mapping as a problem of assigning visibility values to
edges of input Boolean network to minimize the number of nodes in the network. We
describe an algorithm that assigns visibility valtrcs efficiently. We compare our method to the
“xl_cover” algorithm provi (ied by the MIS-pga systcm.
architectures. We first introduce lhc notion of edge visibility. Wc then formulate lhc problem of
finding the area-optimal technology mapping as a problem of assigning visibility values to
edges of input Boolean network to minimize the number of nodes in the network. We
describe an algorithm that assigns visibility valtrcs efficiently. We compare our method to the
“xl_cover” algorithm provi (ied by the MIS-pga systcm.
Abstract
We present an efficient technology mapping method for lookup table-based FPGA architectures. We first introduce lhc notion of edge visibility. Wc then formulate lhc problem of finding the area-optimal technology mapping as a problem of assigning visibility values to edges of input Boolean network to minimize the number of nodes in the network. We describe an algorithm that assigns visibility valtrcs efficiently. We compare our method to the “xl_cover” algorithm provi (ied by the MIS-pga systcm.
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