VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulation and testing based methods. Similarly, statistical timing analysis methods are in three counterpart categories: (1) statistical static timing analysis, (2) probabilistic technique based statistical timing analysis, and (3) Monte Carlo (SPICE) simulation and testing. Leveraging with existing power estimation techniques, I propose signal probability (i.e., the logic one occurrence probability on a net) based statistical timing analysis, for improved accuracy and reduced pessimism over the existing statistical static timing analysis methods, and improved efficiency over Monte Carlo (SPICE) simulation. Experimental results on ISCAS benchmark circuits show that SPSTA computes the means (standard deviations) of the maximum signal arrival times within 5.6% (7.7%), SSTA within 16.5% (46.9%), and STA within 83.0% (132.4%) in average of Monte Carlo simulation results, respectively. More significant accuracy improvements are expected in the presence of increased process and environmental variations.