[PDF][PDF] A scalable hardware render accelerator using a modified scanline algorithm
M Kelley, S Winner, K Gould - … of the 19th annual conference on …, 1992 - dl.acm.org
M Kelley, S Winner, K Gould
Proceedings of the 19th annual conference on Computer graphics and …, 1992•dl.acm.orgA hardware accelerator for 3D ren&ring, based on a mcdifkd scanline algorithm, is
presented. The accelerator renders multiple scanlines in parallel with high efficiency, and is
optimized for integration into systems that suppr [ high speed data streams (such as video).
The architecture has a very high performance/cost ratio, but maintains a low entry cost and a
high degree of scalability—key issues for incorporation in personal computers. The
performance of both the general algorithm and the prototype implementation is analyzed.
presented. The accelerator renders multiple scanlines in parallel with high efficiency, and is
optimized for integration into systems that suppr [ high speed data streams (such as video).
The architecture has a very high performance/cost ratio, but maintains a low entry cost and a
high degree of scalability—key issues for incorporation in personal computers. The
performance of both the general algorithm and the prototype implementation is analyzed.
A hardware accelerator for 3D ren&ring, based on a mcdifkd scanline algorithm, is presented. The accelerator renders multiple scanlines in parallel with high efficiency, and is optimized for integration into systems that suppr [ high speed data streams (such as video). The architecture has a very high performance/cost ratio, but maintains a low entry cost and a high degree of scalability—key issues for incorporation in personal computers. The performance of both the general algorithm and the prototype implementation is analyzed.
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