Black-box identity testing of depth-4 multilinear circuits
S Saraf, I Volkovich - Proceedings of the forty-third annual ACM …, 2011 - dl.acm.org
Proceedings of the forty-third annual ACM symposium on Theory of computing, 2011•dl.acm.org
We study the problem of identity testing for multilinear ΣΠΣΠ (k) circuits, ie multilinear depth-
4 circuits with fan-in k at the top+ gate. We give the first polynomial-time deterministic identity
testing algorithm for such circuits. Our results also hold in the black-box setting. The running
time of our algorithm is (ns) O (k3), where n is the number of variables, s is the size of the
circuit and k is the fan-in of the top gate. The importance of this model arises from [3], where
it was shown that derandomizing black-box polynomial identity testing for general depth-4 …
4 circuits with fan-in k at the top+ gate. We give the first polynomial-time deterministic identity
testing algorithm for such circuits. Our results also hold in the black-box setting. The running
time of our algorithm is (ns) O (k3), where n is the number of variables, s is the size of the
circuit and k is the fan-in of the top gate. The importance of this model arises from [3], where
it was shown that derandomizing black-box polynomial identity testing for general depth-4 …
We study the problem of identity testing for multilinear ΣΠΣΠ(k) circuits, i.e. multilinear depth-4 circuits with fan-in k at the top + gate. We give the first polynomial-time deterministic identity testing algorithm for such circuits. Our results also hold in the black-box setting.
The running time of our algorithm is (ns)O(k3), where n is the number of variables, s is the size of the circuit and k is the fan-in of the top gate. The importance of this model arises from [3], where it was shown that derandomizing black-box polynomial identity testing for general depth-4 circuits implies a derandomization of polynomial identity testing (PIT) for general arithmetic circuits. Prior to our work, the best PIT algorithm for multilinear ΣΠΣΠ(k) circuits [13] ran in quasi-polynomial-time, with the running time being nO(k6 log(k) log2 s ).
We obtain our results by showing a strong structural result for multilinear ΣΠΣΠ(k) circuits that compute the zero polynomial. We show that under some mild technical conditions, any gate of such a circuit must compute a sparse polynomial. We then show how to combine the structure theorem with a result by Klivans and Spielman [17], on the identity testing for sparse polynomials, to yield the full result.
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