This paper presents a cache coherence solution for multiprocessors organized around a single time-shared bus. The solution aims at reduoing bus traffic and hence bus wait time. This in turn inoreaees the overall processor utilization. Unllke most traditional high-performance coherenoe solutions, this solution does not use any global tables. Furthermore, this coherence saheme is modular and easily extensible, requiring no modification of cache modules to add more processors to a systtun. The performance of this scheme is evaluated by using an approximate analysis method. It Is shown that the performance of this scheme is olomely tied uith the miss ratio and the amount of sharing between processors.