Industrial experience with test generation languages for processor verification
M Behm, J Ludden, Y Lichtenstein, M Rimon… - Proceedings of the 41st …, 2004 - dl.acm.org
M Behm, J Ludden, Y Lichtenstein, M Rimon, M Vinov
Proceedings of the 41st annual Design Automation Conference, 2004•dl.acm.orgWe report on our experience with a new test generation language for processor verification.
The verification of two superscalar multiprocessors is described and we show the ease of
expressing complex verification tasks. The cost and benefit are demonstrated: training takes
up to six months; the simulation time required for a desired level of coverage has decreased
by a factor of twenty; the number of escape bugs has been reduced.
The verification of two superscalar multiprocessors is described and we show the ease of
expressing complex verification tasks. The cost and benefit are demonstrated: training takes
up to six months; the simulation time required for a desired level of coverage has decreased
by a factor of twenty; the number of escape bugs has been reduced.
We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the number of escape bugs has been reduced.
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