How fault-tolerant quantum computing benefits from cryo-CMOS technology
HL Chiang, RA Hadi, JF Wang, HC Han… - … IEEE Symposium on …, 2023 - ieeexplore.ieee.org
HL Chiang, RA Hadi, JF Wang, HC Han, JJ Wu, HH Hsieh, JJ Horng, WS Chou, BS Lien…
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI …, 2023•ieeexplore.ieee.orgGiven the limited space and cooling capacity in dilution refrigerators, it is challenging to
scale the number of qubits for a fault-tolerant quantum computer (QC). In this paper, we
study a custom-scaled CMOS technology to overcome the constraints in the dilution
refrigerators. With Cryo-Design/Technology CoOptimization (Cryo-DTCO) in an advanced
node, one can then reduce the control power from 26.8 mW/qubit to 8.4 mW/qubit (∼0.31*).
Projections suggest this may be sufficient to enable error corrections via surface codes for …
scale the number of qubits for a fault-tolerant quantum computer (QC). In this paper, we
study a custom-scaled CMOS technology to overcome the constraints in the dilution
refrigerators. With Cryo-Design/Technology CoOptimization (Cryo-DTCO) in an advanced
node, one can then reduce the control power from 26.8 mW/qubit to 8.4 mW/qubit (∼0.31*).
Projections suggest this may be sufficient to enable error corrections via surface codes for …
Given the limited space and cooling capacity in dilution refrigerators, it is challenging to scale the number of qubits for a fault-tolerant quantum computer (QC). In this paper, we study a custom-scaled CMOS technology to overcome the constraints in the dilution refrigerators. With Cryo-Design/ Technology CoOptimization (Cryo-DTCO) in an advanced node, one can then reduce the control power from 26.8 mW/ qubit to 8.4 mW/ qubit . Projections suggest this may be sufficient to enable error corrections via surface codes for fault-tolerant computing.
ieeexplore.ieee.org
