High performance FPGA-based DMA interface for PCIe
H Kavianipour, S Muschter… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
H Kavianipour, S Muschter, C Bohm
IEEE Transactions on Nuclear Science, 2014•ieeexplore.ieee.orgWe present a data communication suite developed for use in the Track Engine Trigger for
the IceCube Neutrino Observatory at the South Pole. The suite is applicable to any
bidirectional Direct Memory Access (DMA) transfer between FPGA logic and system memory
on a host PC via PCIe. The suite contains a DMA controller firmware, test benches, a Linux
driver and a user application for DMA and Peripheral Input/Output transfers (PIO) into on-
FPGA memory modules and FIFOs. The DMA which is based on the Xilinx'bus master DMA …
the IceCube Neutrino Observatory at the South Pole. The suite is applicable to any
bidirectional Direct Memory Access (DMA) transfer between FPGA logic and system memory
on a host PC via PCIe. The suite contains a DMA controller firmware, test benches, a Linux
driver and a user application for DMA and Peripheral Input/Output transfers (PIO) into on-
FPGA memory modules and FIFOs. The DMA which is based on the Xilinx'bus master DMA …
We present a data communication suite developed for use in the Track Engine Trigger for the IceCube Neutrino Observatory at the South Pole. The suite is applicable to any bidirectional Direct Memory Access (DMA) transfer between FPGA logic and system memory on a host PC via PCIe. The suite contains a DMA controller firmware, test benches, a Linux driver and a user application for DMA and Peripheral Input/Output transfers (PIO) into on-FPGA memory modules and FIFOs. The DMA which is based on the Xilinx' bus master DMA, produces measured transfer speeds up to 748 MB/s (read) and 784 MB/s (write) using the Xilinx VC707 Virtex-7 board. The hardware part of the suite has been verified on different circuit boards with different FPGAs.
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