Bulletin of Electrical Engineering and Informatics, 2021
This paper presents a VHDL design and an FPGA implementation of a direct torque controller (DTC) ... more This paper presents a VHDL design and an FPGA implementation of a direct torque controller (DTC) used to order induction machines (IM). The use of FPGA at high sampling frequency reduces the torque ripple while maintaining the classical DTC control structure. We have adopted a modular approach, by dividing the global entity into a set of elementary blocks designed and implemented separately. The performances of this command are to reduce the torque ripple to 0.01 Nm and the flux ripple to 0.01 wb with a circuit implementing DTC control of 3,256 LEs of complexity and 64 latency clock cycles. To evaluate the performance of our FPGA circuit implementing DTC controller, we have performed a co-simulation platform based on MATLAB/Simulink and Modelsim programs. MATLAB/Simulink was used to simulate the dynamics of the induction machine associated with its inverter and the proposed DTC control strategy was executed under the modelsim software using the VHDL fixed point. We have operated our...
International Review on Modelling and Simulations (IREMOS), 2017
In this paper, we will focus on the VHDL design and the FPGA implementation In the Loop (HIL) of ... more In this paper, we will focus on the VHDL design and the FPGA implementation In the Loop (HIL) of the space-vector Pulse with modulation technique (SVPWM) applied to the three-phase inverter ensuring the speed variation of an asynchronous machine .We will adopt a modular approach, by dividing the global entity into a set of elementary blocks designed and implemented separately. The obtained performances of the proposed architecture of the SVPWM are 1185 LUTs of complexity and 2 latency clock cycles. We have also realized a platform based on the Matlab / Simulink and DSP Builder co-simulation of the speed variation of an asynchronous machine using our architecture, the results obtained enable us to validate our SVPWM circuit.
This paper presents a VHDL design and FPGA implementation of the space-vector pulse-width modulat... more This paper presents a VHDL design and FPGA implementation of the space-vector pulse-width modulation (SVPWM) strategy. This design is made in a way that each block of the architecture is described on a separate entity. The global block is represented using the above entities as components. The proposed architecture for SVPWM is composed of four blocks. After the implantation of each block, we note that the resources consumed by the global entity, knowing that the same circuit is used for the different blocks namely the Stratix II device EP2S15F484C3, are 1185 ALUTs. The execution time of our architecture is two clock cycles.
Proceedings of the 2nd International Conference on Computing and Wireless Communication Systems, 2017
In this paper1, we will be interested in designing, simulating and implementing DSP in Hardware I... more In this paper1, we will be interested in designing, simulating and implementing DSP in Hardware In the Loop (HIL) of the Indirect Rotor Field Oriented Control (IRFOC) of the three-phase asynchronous motor. Simulation and code generation as well as HIL will be performed on the MATLAB / SIMULINK platform, IDE Code Composer Studio and DSP TMS320F28335. The obtained performances from this command are: A zero overrun, a response time in speed of 300ms and a zero static error with respect to the set point and the disturbance similar to the results of the simulation.
Bulletin of Electrical Engineering and Informatics, 2021
This paper presents a VHDL design and an FPGA implementation of a direct torque controller (DTC) ... more This paper presents a VHDL design and an FPGA implementation of a direct torque controller (DTC) used to order induction machines (IM). The use of FPGA at high sampling frequency reduces the torque ripple while maintaining the classical DTC control structure. We have adopted a modular approach, by dividing the global entity into a set of elementary blocks designed and implemented separately. The performances of this command are to reduce the torque ripple to 0.01 Nm and the flux ripple to 0.01 wb with a circuit implementing DTC control of 3,256 LEs of complexity and 64 latency clock cycles. To evaluate the performance of our FPGA circuit implementing DTC controller, we have performed a co-simulation platform based on MATLAB/Simulink and Modelsim programs. MATLAB/Simulink was used to simulate the dynamics of the induction machine associated with its inverter and the proposed DTC control strategy was executed under the modelsim software using the VHDL fixed point. We have operated our...
Bulletin of Electrical Engineering and Informatics, 2021
This paper presents a VHDL design and an FPGA implementation of a direct torque controller (DTC) ... more This paper presents a VHDL design and an FPGA implementation of a direct torque controller (DTC) used to order induction machines (IM). The use of FPGA at high sampling frequency reduces the torque ripple while maintaining the classical DTC control structure. We have adopted a modular approach, by dividing the global entity into a set of elementary blocks designed and implemented separately. The performances of this command are to reduce the torque ripple to 0.01 Nm and the flux ripple to 0.01 wb with a circuit implementing DTC control of 3,256 LEs of complexity and 64 latency clock cycles. To evaluate the performance of our FPGA circuit implementing DTC controller, we have performed a co-simulation platform based on MATLAB/Simulink and Modelsim programs. MATLAB/Simulink was used to simulate the dynamics of the induction machine associated with its inverter and the proposed DTC control strategy was executed under the modelsim software using the VHDL fixed point. We have operated our...
International Review on Modelling and Simulations (IREMOS), 2017
In this paper, we will focus on the VHDL design and the FPGA implementation In the Loop (HIL) of ... more In this paper, we will focus on the VHDL design and the FPGA implementation In the Loop (HIL) of the space-vector Pulse with modulation technique (SVPWM) applied to the three-phase inverter ensuring the speed variation of an asynchronous machine .We will adopt a modular approach, by dividing the global entity into a set of elementary blocks designed and implemented separately. The obtained performances of the proposed architecture of the SVPWM are 1185 LUTs of complexity and 2 latency clock cycles. We have also realized a platform based on the Matlab / Simulink and DSP Builder co-simulation of the speed variation of an asynchronous machine using our architecture, the results obtained enable us to validate our SVPWM circuit.
This paper presents a VHDL design and FPGA implementation of the space-vector pulse-width modulat... more This paper presents a VHDL design and FPGA implementation of the space-vector pulse-width modulation (SVPWM) strategy. This design is made in a way that each block of the architecture is described on a separate entity. The global block is represented using the above entities as components. The proposed architecture for SVPWM is composed of four blocks. After the implantation of each block, we note that the resources consumed by the global entity, knowing that the same circuit is used for the different blocks namely the Stratix II device EP2S15F484C3, are 1185 ALUTs. The execution time of our architecture is two clock cycles.
Proceedings of the 2nd International Conference on Computing and Wireless Communication Systems, 2017
In this paper1, we will be interested in designing, simulating and implementing DSP in Hardware I... more In this paper1, we will be interested in designing, simulating and implementing DSP in Hardware In the Loop (HIL) of the Indirect Rotor Field Oriented Control (IRFOC) of the three-phase asynchronous motor. Simulation and code generation as well as HIL will be performed on the MATLAB / SIMULINK platform, IDE Code Composer Studio and DSP TMS320F28335. The obtained performances from this command are: A zero overrun, a response time in speed of 300ms and a zero static error with respect to the set point and the disturbance similar to the results of the simulation.
Bulletin of Electrical Engineering and Informatics, 2021
This paper presents a VHDL design and an FPGA implementation of a direct torque controller (DTC) ... more This paper presents a VHDL design and an FPGA implementation of a direct torque controller (DTC) used to order induction machines (IM). The use of FPGA at high sampling frequency reduces the torque ripple while maintaining the classical DTC control structure. We have adopted a modular approach, by dividing the global entity into a set of elementary blocks designed and implemented separately. The performances of this command are to reduce the torque ripple to 0.01 Nm and the flux ripple to 0.01 wb with a circuit implementing DTC control of 3,256 LEs of complexity and 64 latency clock cycles. To evaluate the performance of our FPGA circuit implementing DTC controller, we have performed a co-simulation platform based on MATLAB/Simulink and Modelsim programs. MATLAB/Simulink was used to simulate the dynamics of the induction machine associated with its inverter and the proposed DTC control strategy was executed under the modelsim software using the VHDL fixed point. We have operated our...
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