Optical Fiber Communication Conference and National Fiber Optic Engineers Conference, 2009
Elimination of DWDM transponders in an IP over DWDM network is demonstrated, for the first time, ... more Elimination of DWDM transponders in an IP over DWDM network is demonstrated, for the first time, using DWDM XFP MSA transceivers with integrated G.709 framing for OAM management and Forward Error Correction for performance capabilities.
Asia Communications and Photonics Conference 2013, 2013
ABSTRACT A multi-level timing recovery based on the MMSE algorithm and fabricated in a SiGe proce... more ABSTRACT A multi-level timing recovery based on the MMSE algorithm and fabricated in a SiGe process, is shown experimentally to recover accurate symbol timing from a distorted signal produced by a 400-Km uncompensated SMF fiber link.
Abstract—Using a perturbation technique, we propose a new solution to the nonlinear Schrodinger e... more Abstract—Using a perturbation technique, we propose a new solution to the nonlinear Schrodinger equation (NLSE) governing nonlinear light propagation in the optical fiber. The solution is shown to fit the frequency-selective fading model for the wireless channel. We then use this model to derive new lower-bounds on the capacity of nonlinear fiber optic communications, with and without side information. Index Terms — Channel capacity, fiber optics, optical propagation, wavelength division multiplexing. I.
Abstract-We use the method of multiple scales borrowed from perturbation theory to derive a new t... more Abstract-We use the method of multiple scales borrowed from perturbation theory to derive a new time-domain transfer function of the nonlinear fiber-optic wave-division multiplexing (WDM) communications channel. The obtained channel response, derived from the nonlinear Schrodinger equation is shown to be equivalent to the multi-path fading frequency selective channel encountered in wireless links. In the linear regime, the channel response is shown to be equivalent to a standard intersymbol interference (lSI) channel and is used to derive new bounds on the capacity of the dispersive optical fiber channel. I.
This paper presents a 56GS/s 64-way time-interleaved ADC in 28nm CMOS. The ADC can meet the ENOB,... more This paper presents a 56GS/s 64-way time-interleaved ADC in 28nm CMOS. The ADC can meet the ENOB, BW and sampling rate requirements of a 224Gb/s DP-16QAM coherent receiver and is suitable for working as a 56Gb/s PAM-4 analog front-end in optical application. We propose a parametric track-and-hold amplifier and a switched sub-channel buffer to improve the SNR and linearity. The ADC achieves 6.4b ENOB at DC and greater than 5.2b ENOB up to the Nyquist frequency. The prototype utilizes multiple bandwidth enhancing techniques and a hierarchical sampling architecture to enable the 31.5GHz BW and 56GS/s sampling rate, respectively. The power consumption of the entire ADC is 702mW.
ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
A 43.6dB-SNDR 1-GS/s 8-bit single-channel successive-approximation-register (SAR) analog-to-digit... more A 43.6dB-SNDR 1-GS/s 8-bit single-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) using coarse and fine comparators with fully background comparator offset calibration is presented. Low-power coarse comparators and low-noise fine comparators are both employed to improve the comparator power efficiency. Non-binary digital-to-analog converter (DAC) with redundancy is employed to tolerate possible errors in the most-significant-bit (MSB) decisions. A novel comparator offset calibration scheme is proposed to remove the offsets between the different comparators, without slowing down the speed of the SAR conversion. The prototype ADC is implemented in a 28 nm CMOS technology and achieves an ENOB of 6.95 (43.6-dB SNDR) near Nyquist frequency while consuming 3.2 mW, translating into an FOM of 25.87 fJ/conversion-step. To the best of our knowledge, this ADC achieved the highest SNDR among all single-channel SAR ADCs reported that operate above 1GS/s.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
This paper presents a 1-GS/s 3.2-mW 8-bit successive approximation register (SAR) analog-to-digit... more This paper presents a 1-GS/s 3.2-mW 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) using background-calibrated coarse and fine comparators. A coarse and fine comparator scheme is proposed for the bit cycling procedure of MSBs and LSBs to reduce the power consumption. By employing a capacitive digital-to-analog converter (DAC) with redundancy, the decision errors of the coarse comparators due to the thermal noise can be tolerated. Therefore, coarse comparators can have relaxed noise constraint and consume low power. In addition, a novel background calibration method is proposed to align the offsets between different comparators using a reference comparator. This background calibration technique requires no additional bit cycle for comparator calibration, thus improving the ADC’s conversion speed. The prototype ADC is implemented in a 28-nm CMOS technology and achieves an effective number of bits of 6.95 b (signal to noise and distortion ratio (SNDR) of 43.6 dB) near Nyquist frequency with the figure of merit (FOM) of 25.87 fJ/conversion-step. To the best of authors’ knowledge, this ADC achieves the highest SNDR among all single-channel SAR ADCs reported that operate above 1 GS/s.
This paper presents a 31.5-GHz bandwidth (BW) 56-GS/s time-interleaved (TI) analog-to-digital con... more This paper presents a 31.5-GHz bandwidth (BW) 56-GS/s time-interleaved (TI) analog-to-digital converter (ADC) with 5.7-b effective number of bits (ENOB) and 5.2-b ENOB up to 17.5 and 27.1 GHz, respectively. To achieve the ENOB requirement over the entire Nyquist BW in 100-/200-Gb/s digital coherent receivers, several ENOB and BW enhancement techniques are presented. First, a low-noise parametric T/H amplifier is proposed to amplify the sampled signal and improve the SNR of the subsequent sub-channel ADCs. Second, a switched sub-channel buffer is proposed to avoid the distortion caused by the limited BW of the sub-channel buffer during tracking. Finally, multiple BW enhancing techniques are employed. The entire chip is fabricated in the 28-nm CMOS process, occupies an active area of 0.878 mm2, and consumes 702 mW.
Optical Fiber Communication Conference and National Fiber Optic Engineers Conference, 2009
Elimination of DWDM transponders in an IP over DWDM network is demonstrated, for the first time, ... more Elimination of DWDM transponders in an IP over DWDM network is demonstrated, for the first time, using DWDM XFP MSA transceivers with integrated G.709 framing for OAM management and Forward Error Correction for performance capabilities.
Asia Communications and Photonics Conference 2013, 2013
ABSTRACT A multi-level timing recovery based on the MMSE algorithm and fabricated in a SiGe proce... more ABSTRACT A multi-level timing recovery based on the MMSE algorithm and fabricated in a SiGe process, is shown experimentally to recover accurate symbol timing from a distorted signal produced by a 400-Km uncompensated SMF fiber link.
Abstract—Using a perturbation technique, we propose a new solution to the nonlinear Schrodinger e... more Abstract—Using a perturbation technique, we propose a new solution to the nonlinear Schrodinger equation (NLSE) governing nonlinear light propagation in the optical fiber. The solution is shown to fit the frequency-selective fading model for the wireless channel. We then use this model to derive new lower-bounds on the capacity of nonlinear fiber optic communications, with and without side information. Index Terms — Channel capacity, fiber optics, optical propagation, wavelength division multiplexing. I.
Abstract-We use the method of multiple scales borrowed from perturbation theory to derive a new t... more Abstract-We use the method of multiple scales borrowed from perturbation theory to derive a new time-domain transfer function of the nonlinear fiber-optic wave-division multiplexing (WDM) communications channel. The obtained channel response, derived from the nonlinear Schrodinger equation is shown to be equivalent to the multi-path fading frequency selective channel encountered in wireless links. In the linear regime, the channel response is shown to be equivalent to a standard intersymbol interference (lSI) channel and is used to derive new bounds on the capacity of the dispersive optical fiber channel. I.
This paper presents a 56GS/s 64-way time-interleaved ADC in 28nm CMOS. The ADC can meet the ENOB,... more This paper presents a 56GS/s 64-way time-interleaved ADC in 28nm CMOS. The ADC can meet the ENOB, BW and sampling rate requirements of a 224Gb/s DP-16QAM coherent receiver and is suitable for working as a 56Gb/s PAM-4 analog front-end in optical application. We propose a parametric track-and-hold amplifier and a switched sub-channel buffer to improve the SNR and linearity. The ADC achieves 6.4b ENOB at DC and greater than 5.2b ENOB up to the Nyquist frequency. The prototype utilizes multiple bandwidth enhancing techniques and a hierarchical sampling architecture to enable the 31.5GHz BW and 56GS/s sampling rate, respectively. The power consumption of the entire ADC is 702mW.
ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
A 43.6dB-SNDR 1-GS/s 8-bit single-channel successive-approximation-register (SAR) analog-to-digit... more A 43.6dB-SNDR 1-GS/s 8-bit single-channel successive-approximation-register (SAR) analog-to-digital converter (ADC) using coarse and fine comparators with fully background comparator offset calibration is presented. Low-power coarse comparators and low-noise fine comparators are both employed to improve the comparator power efficiency. Non-binary digital-to-analog converter (DAC) with redundancy is employed to tolerate possible errors in the most-significant-bit (MSB) decisions. A novel comparator offset calibration scheme is proposed to remove the offsets between the different comparators, without slowing down the speed of the SAR conversion. The prototype ADC is implemented in a 28 nm CMOS technology and achieves an ENOB of 6.95 (43.6-dB SNDR) near Nyquist frequency while consuming 3.2 mW, translating into an FOM of 25.87 fJ/conversion-step. To the best of our knowledge, this ADC achieved the highest SNDR among all single-channel SAR ADCs reported that operate above 1GS/s.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
This paper presents a 1-GS/s 3.2-mW 8-bit successive approximation register (SAR) analog-to-digit... more This paper presents a 1-GS/s 3.2-mW 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) using background-calibrated coarse and fine comparators. A coarse and fine comparator scheme is proposed for the bit cycling procedure of MSBs and LSBs to reduce the power consumption. By employing a capacitive digital-to-analog converter (DAC) with redundancy, the decision errors of the coarse comparators due to the thermal noise can be tolerated. Therefore, coarse comparators can have relaxed noise constraint and consume low power. In addition, a novel background calibration method is proposed to align the offsets between different comparators using a reference comparator. This background calibration technique requires no additional bit cycle for comparator calibration, thus improving the ADC’s conversion speed. The prototype ADC is implemented in a 28-nm CMOS technology and achieves an effective number of bits of 6.95 b (signal to noise and distortion ratio (SNDR) of 43.6 dB) near Nyquist frequency with the figure of merit (FOM) of 25.87 fJ/conversion-step. To the best of authors’ knowledge, this ADC achieves the highest SNDR among all single-channel SAR ADCs reported that operate above 1 GS/s.
This paper presents a 31.5-GHz bandwidth (BW) 56-GS/s time-interleaved (TI) analog-to-digital con... more This paper presents a 31.5-GHz bandwidth (BW) 56-GS/s time-interleaved (TI) analog-to-digital converter (ADC) with 5.7-b effective number of bits (ENOB) and 5.2-b ENOB up to 17.5 and 27.1 GHz, respectively. To achieve the ENOB requirement over the entire Nyquist BW in 100-/200-Gb/s digital coherent receivers, several ENOB and BW enhancement techniques are presented. First, a low-noise parametric T/H amplifier is proposed to amplify the sampled signal and improve the SNR of the subsequent sub-channel ADCs. Second, a switched sub-channel buffer is proposed to avoid the distortion caused by the limited BW of the sub-channel buffer during tracking. Finally, multiple BW enhancing techniques are employed. The entire chip is fabricated in the 28-nm CMOS process, occupies an active area of 0.878 mm2, and consumes 702 mW.
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Papers by Salam Elahmadi