NOTICE WARNING CONCERNING COPYRIGHT RESTRICTIONS: The copyright law of the United States (title 1... more NOTICE WARNING CONCERNING COPYRIGHT RESTRICTIONS: The copyright law of the United States (title 17, U.S. Code) governs the making of photocopies or other reproductions of copyrighted material. Any copying of this document without permission of its author may be prohibited by law.
The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four... more The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four-transistor dynamic cell. Sense amplifiers are used to reduce access time. Bootstrapped logic reduces power dissipation. Experimental results indicate a typical cycle time of 160ns and power dissipation of 160mW. /
The quiescent current testing (IDDQ testing) for CMOS ICs provides several advantages over other ... more The quiescent current testing (IDDQ testing) for CMOS ICs provides several advantages over other testing methods. However, the future of IDDQ testing is threatened by increased sub-threshold leakage current for new technologies. The conventional pass/fail limit setting methodology cannot survive in its present form. In this paper we evaluate two statistical outlier rejection methods – the Chauvenet’s criterion and the Tukey test – for their applicability to IDDQ testing. They are compared with the static-threshold method. The results of the analysis of application of these methods to the SEMATECH data are presented.
This work presents a methodology to identify integrated circuit yield detractors using SRAM funct... more This work presents a methodology to identify integrated circuit yield detractors using SRAM functional test results in combination with a defect-bitmap dictionary. We investigate the accuracy of the defect classification under different forms of voltage testing and current testing. In particular we investigate the benefit of using multiple Iddq current levels calibrated to remove normal parametric variations. We also investigate the effects of unmodeled defects and the ability to identify cases off certain and uncertain diagnosis. We have experimentally validated our approach using a production microprocessor cache
... by Sagar Suresh Sabade , Duncan Walker , Vivek Sarin , Donald ... MISC{Sabade04bymultiple, au... more ... by Sagar Suresh Sabade , Duncan Walker , Vivek Sarin , Donald ... MISC{Sabade04bymultiple, author = {Sagar Suresh Sabade and Duncan Walker and Vivek Sarin and Donald Friesen and Henry Taylor}, title = {BY MULTIPLE PARAMETER CORRELATION}, year = {2004} }. ...
The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four... more The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four-transistor dynamic cell. Sense amplifiers are used to reduce access time. Bootstrapped logic reduces power dissipation. Experimental results indicate a typical cycle time of ...
ABSTRACT This paper describes the DEfect to FAult Mapper (DEFAM), and its use in integrated circu... more ABSTRACT This paper describes the DEfect to FAult Mapper (DEFAM), and its use in integrated circuit test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects on a design during the manufacturing process, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the required analysis effort. It also reports faults in terms of the design hierarchy, which is essential for many applications. Yield analysis results are given for CMOS designs of up to 164K transistors. Test quality analysis results are given for an adder module.
Proceedings of the 1998 Acm Sigda Sixth International Symposium on Field Programmable Gate Arrays, 1998
ABSTRACT This paper presents a vector generation approach for testing interconnects in configurab... more ABSTRACT This paper presents a vector generation approach for testing interconnects in configurable (SRAM-based) Field Programmable Gate Arrays (FPGAs). The proposed approach detects bridging faults and is based on quiescent current (IDDQ monitoring. Compared with previous voltage-based methods, IDDQ testing has the advantage of utilizing a small number of programming phases for configuring the FPGA during the test process with negligible observability requirements, even under multiple faults. Algorithms for test generation which exploit the homogeneous nature of the FPGA array, are described. An example using the XC4000 is described in detail. For testing the XC4000 series interconnect, a total of 20 phases and 11 vectors are required: 11 phases for S (switch) block testing, and 9 phases for C (connection) block testing.
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993
This paper describes the DEFAM defect to fault mapper, and its use in test quality analysis and y... more This paper describes the DEFAM defect to fault mapper, and its use in test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects in the manufacturing process on a design, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the simulation effort needed. It also reports
ABSTRACT Dynamic compaction is an effective way to reduce the number of test patterns while maint... more ABSTRACT Dynamic compaction is an effective way to reduce the number of test patterns while maintaining high fault coverage. This paper proposes a new dynamic compaction algorithm for generating compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting assignments together during test generation. Experimental results for ISCAS89 benchmark circuits and two industry circuits show that the pattern count of KLPG can be significantly reduced (up to 3x compared to static compaction) using the proposed method. The pattern count after dynamic compaction is comparable to the number of transition fault tests, while achieving higher test quality.
NOTICE WARNING CONCERNING COPYRIGHT RESTRICTIONS: The copyright law of the United States (title 1... more NOTICE WARNING CONCERNING COPYRIGHT RESTRICTIONS: The copyright law of the United States (title 17, U.S. Code) governs the making of photocopies or other reproductions of copyrighted material. Any copying of this document without permission of its author may be prohibited by law.
The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four... more The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four-transistor dynamic cell. Sense amplifiers are used to reduce access time. Bootstrapped logic reduces power dissipation. Experimental results indicate a typical cycle time of 160ns and power dissipation of 160mW. /
The quiescent current testing (IDDQ testing) for CMOS ICs provides several advantages over other ... more The quiescent current testing (IDDQ testing) for CMOS ICs provides several advantages over other testing methods. However, the future of IDDQ testing is threatened by increased sub-threshold leakage current for new technologies. The conventional pass/fail limit setting methodology cannot survive in its present form. In this paper we evaluate two statistical outlier rejection methods – the Chauvenet’s criterion and the Tukey test – for their applicability to IDDQ testing. They are compared with the static-threshold method. The results of the analysis of application of these methods to the SEMATECH data are presented.
This work presents a methodology to identify integrated circuit yield detractors using SRAM funct... more This work presents a methodology to identify integrated circuit yield detractors using SRAM functional test results in combination with a defect-bitmap dictionary. We investigate the accuracy of the defect classification under different forms of voltage testing and current testing. In particular we investigate the benefit of using multiple Iddq current levels calibrated to remove normal parametric variations. We also investigate the effects of unmodeled defects and the ability to identify cases off certain and uncertain diagnosis. We have experimentally validated our approach using a production microprocessor cache
... by Sagar Suresh Sabade , Duncan Walker , Vivek Sarin , Donald ... MISC{Sabade04bymultiple, au... more ... by Sagar Suresh Sabade , Duncan Walker , Vivek Sarin , Donald ... MISC{Sabade04bymultiple, author = {Sagar Suresh Sabade and Duncan Walker and Vivek Sarin and Donald Friesen and Henry Taylor}, title = {BY MULTIPLE PARAMETER CORRELATION}, year = {2004} }. ...
The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four... more The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four-transistor dynamic cell. Sense amplifiers are used to reduce access time. Bootstrapped logic reduces power dissipation. Experimental results indicate a typical cycle time of ...
ABSTRACT This paper describes the DEfect to FAult Mapper (DEFAM), and its use in integrated circu... more ABSTRACT This paper describes the DEfect to FAult Mapper (DEFAM), and its use in integrated circuit test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects on a design during the manufacturing process, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the required analysis effort. It also reports faults in terms of the design hierarchy, which is essential for many applications. Yield analysis results are given for CMOS designs of up to 164K transistors. Test quality analysis results are given for an adder module.
Proceedings of the 1998 Acm Sigda Sixth International Symposium on Field Programmable Gate Arrays, 1998
ABSTRACT This paper presents a vector generation approach for testing interconnects in configurab... more ABSTRACT This paper presents a vector generation approach for testing interconnects in configurable (SRAM-based) Field Programmable Gate Arrays (FPGAs). The proposed approach detects bridging faults and is based on quiescent current (IDDQ monitoring. Compared with previous voltage-based methods, IDDQ testing has the advantage of utilizing a small number of programming phases for configuring the FPGA during the test process with negligible observability requirements, even under multiple faults. Algorithms for test generation which exploit the homogeneous nature of the FPGA array, are described. An example using the XC4000 is described in detail. For testing the XC4000 series interconnect, a total of 20 phases and 11 vectors are required: 11 phases for S (switch) block testing, and 9 phases for C (connection) block testing.
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993
This paper describes the DEFAM defect to fault mapper, and its use in test quality analysis and y... more This paper describes the DEFAM defect to fault mapper, and its use in test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects in the manufacturing process on a design, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the simulation effort needed. It also reports
ABSTRACT Dynamic compaction is an effective way to reduce the number of test patterns while maint... more ABSTRACT Dynamic compaction is an effective way to reduce the number of test patterns while maintaining high fault coverage. This paper proposes a new dynamic compaction algorithm for generating compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting assignments together during test generation. Experimental results for ISCAS89 benchmark circuits and two industry circuits show that the pattern count of KLPG can be significantly reduced (up to 3x compared to static compaction) using the proposed method. The pattern count after dynamic compaction is comparable to the number of transition fault tests, while achieving higher test quality.
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Papers by Hank Walker